For the PVT-class hardware we have increased the memory size of
this device to 2 GiB. Adjust the device model accordingly.
Signed-off-by: Patrick Williams
---
hw/arm/aspeed.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index
For the PVT-class hardware we have increased the memory size of
this device to 2 GiB. Adjust the device model accordingly.
Signed-off-by: Patrick Williams
---
hw/arm/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 7d2162c6ed
dded (in reply to patch 8) support for the w25q01jvq chip.
Tested-by: Patrick Williams
--
Patrick Williams
signature.asc
Description: PGP signature
Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp`
Signed-off-by: Patrick Williams
---
hw/block/m25p80.c | 3 ++-
hw/block/m25p80_sfdp.c | 36 ++
pin .
This discussion about SMC reminded me of something that might be leading
to the issues we're seeing. Our hardware implementation uses the same
GPIOs as one of the SMCs and doesn't use the SMC. It could be that both
QEMU models (the SPI-GPIO and the SMC) are trying to grab the same
GPIO
for many SPI protocols, other than flash devices, including the one
used for TPMs.
In order to connect to SPI-based TPMs on an Aspeed chip, you have to use
the SPI-GPIO method.
--
Patrick Williams
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Description: PGP signature
at improving the command line argument to support:
>
>-drive file=,format=raw,id=drive0 -device
> mx66l1g45g,bus=ssi.0,drive=drive0
>
> which we would clearly define the topology. Adding a cs=[0-5] or and
> addr=[0-5] is the next step.
Seems fine to me.
--
Patrick Williams
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Description: PGP signature
-facebook-bletchley.dts?id=a8c729e966c4e9d033242d948b0e53c2a62d32e2
2.
https://github.com/openbmc/openbmc/commit/b9432b980d7f63f7512ffbcc7124386ba896dfc6
3.
https://github.com/openbmc/linux/commit/25b566b9a9d7f5d4f10c1b7304007bdb286eefd7
Signed-off-by: Patrick Williams
---
hw/arm/aspeed.c | 77
Generally all BMCs will use the fmc_model to hold their own flash
and most will have a spi_model to hold the managed system's flash,
but not all systems do. Add a simple NULL check to allow a system
to set the spi_model as NULL to indicate it should not be instantiated.
Signed-off-by: Patrick
The w25q01jvq is a 128MB part. Support is being added to the kernel[1]
and the two have been tested together.
1. https://lore.kernel.org/lkml/2022022209.23108-1-potin@quantatw.com/
Signed-off-by: Patrick Williams
Cc: Potin Lai
---
hw/block/m25p80.c | 1 +
1 file changed, 1 insertion
On Thu, Sep 02, 2021 at 06:19:53PM +0200, Cédric Le Goater wrote:
> On 9/2/21 5:46 PM, Patrick Williams wrote:
> > On Thu, Sep 02, 2021 at 03:12:12PM +, Peter Delevoryas wrote:
> The pca954x muxes are supported and these devices :
Oh! Is that support relatively new? It
2C devices of the machine ?
>
> Yeah sure! I’ll follow up with that.
>
The fuji DTS is available upstream:
https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts
I found that when I did Sonora Pass there were a number of unsupported i2c
devices (ie. devices without QEMU models) but most of them were behind muxes,
which are similarly non-supported. You'll see a pretty large fan-out in the i2c
busses of that DTS. I don't see anything obvious in the DTS that is directly
connected except for the muxes.
--
Patrick Williams
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Description: PGP signature
that worked too.
>
> Signed-off-by: Peter Delevoryas
> ---
> hw/arm/aspeed.c | 1 +
> hw/arm/aspeed_ast2600.c | 11 +++
> hw/arm/aspeed_soc.c | 9 ++---
> include/hw/arm/aspeed.h | 1 +
> 4 files changed, 15 insertions(+), 7 deletions(-)
>
Reviewed-by: Patrick Williams
--
Patrick Williams
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Description: PGP signature
On Mon, May 11, 2020 at 11:54:42AM +0100, Peter Maydell wrote:
> On Wed, 6 May 2020 at 19:32, Patrick Williams wrote:
> Looking up through the thread I can't find the email where
> Amithash gave his reviewed-by tag -- did I miss it?
I probably shouldn't have done this. I asked Ami
/aspeed-bmc-facebook-sonorapass.dts
Booted a test image of http://github.com/facebook/openbmc to login
prompt.
Signed-off-by: Patrick Williams
Reviewed-by: Amithash Prasad
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 77 +
1 file changed, 77
On Wed, May 06, 2020 at 06:06:34PM +, Amithash Prasad wrote:
> >> + mc->desc = "OpenPOWER SonoraPass BMC (ARM1176)";
> Open Compute Project?
Oops. Yeah, this is not an OpenPOWER machine. Will send a v3.
--
Patrick Williams
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Description: PGP signature
/aspeed-bmc-facebook-sonorapass.dts
Booted a test image of http://github.com/facebook/openbmc to login
prompt.
Signed-off-by: Patrick Williams
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 77 +
1 file changed, 77 insertions(+)
diff --git a/hw
/aspeed-bmc-facebook-sonorapass.dts
Booted a test image of http://github.com/facebook/openbmc to login
prompt.
Signed-off-by: Patrick Williams
---
hw/arm/aspeed.c | 76 +
1 file changed, 76 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
I think one possible way is to clear the software tlb on entry to thetransaction and disable (not install any translations) the softwareTLB till the end of the transaction.In the softmmu helper functions, the memory addresses as well asvalue can then be tracked in a hashtable and committed to
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