Re: [Qemu-devel] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions

2016-10-24 Thread Rajalakshmi Srinivasaraghavan
On 09/28/2016 11:15 AM, Rajalakshmi Srinivasaraghavan wrote: From: Hariharan T.S Attached updatde patch based on comments on vextu[bhw]lx. -- Thanks Rajalakshmi S >From f027eb4903b89720634423c335e3688cf1e8632d Mon Sep 17 00:00:00 2001 From: Rajalakshmi Srinivasaraghavan Date: Mon, 24

Re: [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions

2016-10-24 Thread Rajalakshmi Srinivasaraghavan
On 10/05/2016 10:51 AM, Rajalakshmi Srinivasaraghavan wrote: On 09/28/2016 10:24 PM, Richard Henderson wrote: On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote: +#if defined(HOST_WORDS_BIGENDIAN) +#define VEXTULX_DO(name, elem) \ +target_ulong

Re: [Qemu-devel] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions

2016-10-04 Thread Rajalakshmi Srinivasaraghavan
On 09/28/2016 10:12 PM, Richard Henderson wrote: On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote: +val = tcg_const_i64(10);\ Rename this "ten" for clarity? +z = tcg_c

Re: [Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions

2016-10-04 Thread Rajalakshmi Srinivasaraghavan
On 09/28/2016 10:24 PM, Richard Henderson wrote: On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote: +#if defined(HOST_WORDS_BIGENDIAN) +#define VEXTULX_DO(name, elem) \ +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b

[Qemu-devel] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instructions

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
The following vector instructions are added from ISA 3.0. vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |2 ++ target

[Qemu-devel] [PATCH 4/6] target-ppc: fix invalid mask - cmpl, bctar

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
From: Avinesh Kumar cmpl: invalid bit mask should be 0x0041 bctar: invalid bit mask should be 0xE000 Signed-off-by: Avinesh Kumar Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/translate.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a

[Qemu-devel] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
Quadword VX-form Signed-off-by: Vasant Hegde [ Add GEN_VXFORM_DUAL_EXT with invalid bit mask ] Signed-off-by: Nikunj A Dadhania Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/translate/vmx-impl.inc.c | 74 +++ target-ppc/translate/vmx-ops.inc.c

[Qemu-devel] [PATCH 0/6] POWER9 TCG enablement - part5

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
This series contains 15 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector multiply instructions. vmul10uq : Vector Multiply-by-10 Unsigned Quadword vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword vmul10cuq : Vector M

[Qemu-devel] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
From: Hariharan T.S vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form Signed-off-by: Hariharan T.S. Signed-off-by: Avinesh Kumar Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
From: Avinesh Kumar vextublx: Vector Extract Unsigned Byte Left vextuhlx: Vector Extract Unsigned Halfword Left vextuwlx: Vector Extract Unsigned Word Left Signed-off-by: Avinesh Kumar [ Remove else part in helper ] Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h

[Qemu-devel] [PATCH 5/6] target-ppc: add vector compare not equal instructions

2016-09-27 Thread Rajalakshmi Srinivasaraghavan
The following vector compare not equal instructions are added from ISA 3.0. vcmpneb - Vector Compare Not Equal Byte vcmpneh - Vector Compare Not Equal Halfword vcmpnew - Vector Compare Not Equal Word Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |6

[Qemu-devel] [PATCH v6 2/5] target-ppc: add vector extract instructions

2016-09-05 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH v6 3/5] target-ppc: add vector count trailing zeros instructions

2016-09-05 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH v6 4/5] target-ppc: add vector bit permute doubleword instruction

2016-09-05 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 20 target-ppc/translate/vmx-impl.inc.c |1 + target-ppc/translate/vmx-ops.inc.c |1 + 4

[Qemu-devel] [PATCH v6 0/5] POWER9 TCG enablement - part3

2016-09-05 Thread Rajalakshmi Srinivasaraghavan
This series contains 14 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector insert instructions. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doub

[Qemu-devel] [PATCH v6 5/5] target-ppc: add vector permute right indexed instruction

2016-09-05 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.inc.c | 18 ++ target-ppc/translate/vmx

[Qemu-devel] [PATCH v6 1/5] target-ppc: add vector insert instructions

2016-09-05 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4

Re: [Qemu-devel] [PATCH v5 2/5] target-ppc: add vector extract instructions

2016-09-02 Thread Rajalakshmi Srinivasaraghavan
On 09/01/2016 09:38 PM, Richard Henderson wrote: On 08/31/2016 11:36 PM, Rajalakshmi Srinivasaraghavan wrote: +#if defined(HOST_WORDS_BIGENDIAN) +#define VEXTRACT(suffix, element)\ +void helper_vextract##suffix(ppc_avr_t *r, ppc_avr_t *b

[Qemu-devel] [PATCH v5 4/5] target-ppc: add vector bit permute doubleword instruction

2016-08-31 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 20 target-ppc/translate/vmx-impl.inc.c |1 + target-ppc/translate/vmx-ops.inc.c |1 + 4

[Qemu-devel] [PATCH v5 5/5] target-ppc: add vector permute right indexed instruction

2016-08-31 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.inc.c | 18 ++ target-ppc/translate/vmx

[Qemu-devel] [PATCH v5 1/5] target-ppc: add vector insert instructions

2016-08-31 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4

[Qemu-devel] [PATCH v5 3/5] target-ppc: add vector count trailing zeros instructions

2016-08-31 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH v5 0/5] POWER9 TCG enablement - part3

2016-08-31 Thread Rajalakshmi Srinivasaraghavan
This series contains 14 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector insert instructions. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doub

[Qemu-devel] [PATCH v5 2/5] target-ppc: add vector extract instructions

2016-08-31 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH v4 3/5] target-ppc: add vector count trailing zeros instructions

2016-08-24 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH v4 5/5] target-ppc: add vector permute right indexed instruction

2016-08-24 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.inc.c | 18 ++ target-ppc/translate/vmx

[Qemu-devel] [PATCH v4 4/5] target-ppc: add vector bit permute doubleword instruction

2016-08-24 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 20 target-ppc/translate/vmx-impl.inc.c |1 + target-ppc/translate/vmx-ops.inc.c |1 + 4

[Qemu-devel] [PATCH v4 2/5] target-ppc: add vector extract instructions

2016-08-24 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH v4 1/5] target-ppc: add vector insert instructions

2016-08-24 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4

[Qemu-devel] [PATCH v4 0/5] POWER9 TCG enablement - part3

2016-08-24 Thread Rajalakshmi Srinivasaraghavan
This series contains 14 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector insert instructions. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doub

Re: [Qemu-devel] [PATCH v3 1/5] target-ppc: add vector insert instructions

2016-08-18 Thread Rajalakshmi Srinivasaraghavan
On 08/16/2016 09:48 AM, David Gibson wrote: On Thu, Aug 11, 2016 at 01:06:44PM +0530, Rajalakshmi Srinivasaraghavan wrote: The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd

Re: [Qemu-devel] [PATCH v3 5/5] target-ppc: add vector permute right indexed instruction

2016-08-16 Thread Rajalakshmi Srinivasaraghavan
On 08/16/2016 10:15 AM, David Gibson wrote: Why do you need this gen_vpermr() function while there isn't a matching gen_vperm()? vperm is handled as part of GEN_VAFORM_PAIRED(vsel, vperm, 21) However the opcode format of vpermr cannot be combined with any other instruction of VA form. -- Th

[Qemu-devel] [PATCH v3 5/5] target-ppc: add vector permute right indexed instruction

2016-08-11 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.c | 18 ++ target-ppc/translate/vmx-ops.c |1 + 4

[Qemu-devel] [PATCH v3 2/5] target-ppc: add vector extract instructions

2016-08-11 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH v3 0/5] POWER9 TCG enablement - part3

2016-08-11 Thread Rajalakshmi Srinivasaraghavan
This series contains 14 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector insert instructions. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doub

[Qemu-devel] [PATCH v3 4/5] target-ppc: add vector bit permute doubleword instruction

2016-08-11 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 22 ++ target-ppc/translate/vmx-impl.c |1 + target-ppc/translate/vmx-ops.c |1 + 4 files changed, 25

[Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing zeros instructions

2016-08-11 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH v3 1/5] target-ppc: add vector insert instructions

2016-08-11 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4

Re: [Qemu-devel] [PATCH v2 1/5] target-ppc: add vector insert instructions

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
On 08/09/2016 11:50 PM, Richard Henderson wrote: On 08/09/2016 03:42 PM, Rajalakshmi Srinivasaraghavan wrote: +for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ +result.element[i] = r->element[i]; \ + } \ m

[Qemu-devel] [PATCH v2 5/5] target-ppc: add vector permute right indexed instruction

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.c | 18 ++ target-ppc/translate/vmx-ops.c |1 + 4

[Qemu-devel] [PATCH v2 4/5] target-ppc: add vector bit permute doubleword instruction

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 20 target-ppc/translate/vmx-impl.c |1 + target-ppc/translate/vmx-ops.c |1 + 4 files changed, 23

[Qemu-devel] [PATCH v2 3/5] target-ppc: add vector count trailing zeros instructions

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH v2 1/5] target-ppc: add vector insert instructions

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4 +++ target

[Qemu-devel] [PATCH v2 2/5] target-ppc: add vector extract instructions

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH 0/5] POWER9 TCG enablement - part3

2016-08-09 Thread Rajalakshmi Srinivasaraghavan
and vextract. * Correct typecast for vctz. * Computation of index rearranged for vpermr. * Assignment of perm moved out of inner loop in vbpermd. Rajalakshmi Srinivasaraghavan (5): target-ppc: add vector insert instructions target-ppc: add vector extract instructions target-ppc: add vector

[Qemu-devel] [PATCH v1 3/5] target-ppc: add vector count trailing zeros instructions

2016-08-04 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH v1 0/5] POWER9 TCG enablement - part3

2016-08-04 Thread Rajalakshmi Srinivasaraghavan
This series contains 14 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector insert instructions. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doub

[Qemu-devel] [PATCH v1 2/5] target-ppc: add vector extract instructions

2016-08-04 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH v1 1/5] target-ppc: add vector insert instructions

2016-08-04 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4

[Qemu-devel] [PATCH v1 5/5] target-ppc: add vector permute right indexed instruction

2016-08-04 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.c | 18 ++ target-ppc/translate/vmx-ops.c |1 + 4

[Qemu-devel] [PATCH v1 4/5] target-ppc: add vector bit permute doubleword instruction

2016-08-04 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 20 target-ppc/translate/vmx-impl.c |1 + target-ppc/translate/vmx-ops.c |1 + 4 files changed, 23

Re: [Qemu-devel] [PATCH 1/5] target-ppc: add vector insert instructions

2016-08-02 Thread Rajalakshmi Srinivasaraghavan
On 08/03/2016 07:07 AM, David Gibson wrote: On Mon, Aug 01, 2016 at 12:49:38PM +0530, Rajalakshmi Srinivasaraghavan wrote: The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd

[Qemu-devel] [PATCH 4/5] target-ppc: add vector bit permute doubleword instruction

2016-08-01 Thread Rajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 20 target-ppc/translate/vmx-impl.c |1 + target-ppc/translate/vmx-ops.c |1 + 4 files changed, 23

[Qemu-devel] [PATCH 5/5] target-ppc: add vector permute right indexed instruction

2016-08-01 Thread Rajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |1 + target-ppc/int_helper.c | 23 +++ target-ppc/translate/vmx-impl.c | 18 ++ target-ppc/translate/vmx-ops.c |1 + 4

[Qemu-devel] [PATCH 2/5] target-ppc: add vector extract instructions

2016-08-01 Thread Rajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan

[Qemu-devel] [PATCH 3/5] target-ppc: add vector count trailing zeros instructions

2016-08-01 Thread Rajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi

[Qemu-devel] [PATCH 1/5] target-ppc: add vector insert instructions

2016-08-01 Thread Rajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan --- target-ppc/helper.h |4

[Qemu-devel] [PATCH 0/5] POWER9 TCG enablement - part3

2016-08-01 Thread Rajalakshmi Srinivasaraghavan
This series contains 14 new instructions for POWER9 described in ISA3.0. Patches: 01: Adds vector insert instructions. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doub