On Mon, Jun 13, 2016 at 04:16:02PM +0100, Peter Maydell wrote:
> On 13 June 2016 at 15:45, Daniel P. Berrange wrote:
> > On Mon, Jun 13, 2016 at 03:11:08PM +0100, Peter Maydell wrote:
> >> QEMU currently allocates coroutine stacks with a plain g_malloc(),
> >> which makes them r/w but not exec. T
On Mon, Oct 15, 2007 at 04:05:14PM +0100, Thiemo Seufer wrote:
> I found Qemu/MIPS locks up in the emulated kernel's calibrate_delay
> function. Switching the kernel option off works around the problem.
I still haven't patched up the issue which was causing the problem for
Aurel. Is the slow exe
On Tue, Oct 02, 2007 at 10:57:24PM +0200, Aurelien Jarno wrote:
> From: Aurelien Jarno <[EMAIL PROTECTED]>
> Date: Tue, 02 Oct 2007 22:57:24 +0200
> To: Alan Cox <[EMAIL PROTECTED]>
> CC: qemu-devel@nongnu.org, [EMAIL PROTECTED]
> Subject: Re: [Qemu-devel] QEMU/MIPS & dyntick kernel
> Content-Type:
On Wed, Sep 26, 2007 at 08:25:18PM +0400, Alexander Voropay wrote:
> >>>- QEMU malta emulation is not really complete, to put it mildly
> >>Out of curiosity, what parts did you miss?
> >Like, for example, the PCI stuff. So I can use the network card.
>
> PCI stuff in the QEMU/Malta works fine, bu
On Sun, Jun 17, 2007 at 10:06:55AM +0200, Geert Uytterhoeven wrote:
> I guess it's just the printk buffer that's being output again to the new
> console, when the console subsystem switches from early console to real
> console.
Correct.
Ralf
Hi Fabrice,
A sequence like
addiu $r0, $r0, 1
addi$r0, $r0, -1
would result in an integer overflow exception on MIPS targets.
This test fixes the test for a signed overflow done by the add, addi,
sub and subi instructions.
target-mips/op.c | 18 +-
1 fi
The count / compare interrupt is wired to the CPU's internal interrupt
controller, not a PIC.
hw/mips_r4k.c| 10 --
target-mips/helper.c | 12 +++-
2 files changed, 19 insertions(+), 3 deletions(-)
Index: qemu-mips/hw/mips_r4k.c
===
Add i8259 PIT to the MIPS configuration. Not that the counter / compare
interrupt isn't nicer but the i8259 unfortunately a common peripheral in
MIPS systems and so it's probably a piece of code want just in case.
Makefile.target |4 ++--
hw/mips_r4k.c |3 +++
2 files changed, 5 insert
Only take interrupts that are actually enabled in the CPU's interrupt mask
in c0_status.
cpu-exec.c |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: qemu-mips/cpu-exec.c
===
--- qemu-mips.orig/cpu-exec.c
+++ qemu-mip
On Mon, Jun 13, 2005 at 02:47:48PM +0200, Hetz Ben Hamo wrote:
> Full system to boot Irix?
That would require emulation of an IRIX-supported platform. Not undoable -
others have already gotten firmware as complex as the SGI ARC [1]
firmware to run on other emulators, I think it was mips64emul.
On Mon, Jun 13, 2005 at 12:44:09PM +0100, Dominic Sweetman wrote:
> > Known bugs:
> >
> > o ll/sc don't use a ll_bit like the real hardware thus right now any atomic
> >functions aren't really atomic.
>
> I suppose you know that the CPUs all implement "break link on
> exception" by zeroing
On Mon, Jun 13, 2005 at 02:50:37PM +0300, Timo Savola wrote:
> Are there any plans for supporting user-mode MIPS emulation?
At some point certainly but right now my priority is full system emulation.
Ralf
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I've posted updated Qemu patches on
ftp://ftp.linux-mips.org/pub/linux/mips/qemu
http://www.linux-mips.org/wiki/index.php/Qemu
Enhancements over last week's patches:
o The count/compare interrupt will now properly be delivered.
o mfc0 will now return the proper value for the EXL and ERL fl
On Tue, Jun 07, 2005 at 09:08:57PM +0200, Jocelyn Mayer wrote:
> > Oh, I've created a small Qemu/MIPS page on the Linux/MIPS Wiki at
> > http://www.linux-mips.org/wiki/index.php/Qemu. It's a wiki so please feel
> > free to edit.
I've just put patches on that page.
> It would be great to publish
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