) is to be
specified in LE format.
(e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD, Byte[75]=0xAB).
Signed-off-by: Saif Abrar
---
v1 -> v2: Updated the commit message to mention 'properties' instead of 'CLI
options'.
hw/nvme/ctrl.c | 44
hw/nvme/nvme.
) is to be
specified in LE format.
(e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD, Byte[75]=0xAB).
Signed-off-by: Saif Abrar
---
hw/nvme/nvme.h | 5 +
hw/nvme/ctrl.c | 44
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/hw/nvme/nvme.
= PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset
value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
On 3/21/24 11:04, Saif Abrar wrote:
Add a method to reset the value of LSI Sour
= PPC_BITMASK(4, 12);
Is this mask the default value for HW ?
Yes, the spec defines the bits[04:12] of LSI Source ID having reset
value: 0x1FF
Regards,
Saif
On 25-03-2024 07:04 pm, Cédric Le Goater wrote:
On 3/21/24 11:04, Saif Abrar wrote:
Add a method to reset the value of LSI Sour
.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 57 +-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 4e3a6b37f9..7b3d75bae6 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host
Add a method to reset the value of LSI Source-ID.
Mask off LSI source-id based on number of interrupts in the big/small PHB.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host
.
This will set the bits in the reg PHB_PBL_ERR_STATUS.
Reset the PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET.
Verify that the sticky bits in the PHB_PBL_ERR_STATUS reg are still set.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 156
PHB updates the register PCIE Link-Control-2.
Set the write-mask bits for TLS, ENTER_COMP, TX_MARGIN,
HASD, MOD_COMP, COMP_SOS and COMP_P_DE.
Signed-off-by: Saif Abrar
---
hw/pci/pcie.c | 6 ++
include/standard-headers/linux/pci_regs.h | 3 +++
2 files changed, 9
Implement write-1-to-clear and write-X-to-clear logic.
Update registers with silent simple read and write.
Return all 1's when an unimplemented/reserved register is read.
Test that reading address 0x0 returns all 1's (i.e. -1).
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c
New qtest TB added for PHB4.
TB reads PHB Version register and asserts that
bits[24:31] have value 0xA5.
Signed-off-by: Saif Abrar
---
tests/qtest/meson.build | 1 +
tests/qtest/pnv-phb4-test.c | 74 +
2 files changed, 75 insertions(+)
create mode
and return the updated value.
Tested the registers PHB_DMA_SYNC, PHB_PCIE_HOTPLUG_STATUS, PHB_PCIE_LMR,
PHB_PCIE_DLP_TRWCTL, PHB_LEM_ERROR_AND_MASK and PHB_LEM_ERROR_OR_MASK
by writing all 1's and reading back the value.
The WO bits in these registers should read back as 0.
Signed-off-by: Saif Abrar
interrupts
Also, a new testbench for PHB4 model is added that does XSCOM read/writes
to various registers of interest and verifies the values.
Regards.
Saif Abrar (10):
qtest/phb4: Add testbench for PHB4
pnv/phb4: Add reset logic to PHB4
pnv/phb4: Implement sticky reset logic in PHB4
Add a method to be invoked on QEMU reset.
Also add CFG and PBL core-blocks reset logic using
appropriate bits of PHB_PCIE_CRESET register.
Tested by reading the reset value of a register.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 104
Get the current link-status from PCIE macro.
Extract link-speed and link-width from the link-status
and set in the DLP training control (PCIE_DLP_TCR) register.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions
IODA PCT table (#3) is implemented
without any functionality, being a debug table.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 6 ++
include/hw/pci-host/pnv_phb4.h | 2 ++
include/hw/pci-host/pnv_phb4_regs.h | 1 +
3 files changed, 9 insertions(+)
diff --git
Current value of timeout=0.1 is sometimes too tight.
Bump timeout to 0.3 to avoid test failures.
Signed-off-by: Saif Abrar
---
tests/qemu-iotests/tests/iothreads-stream | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/tests/iothreads-stream
b/tests/qemu
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abrar
Reviewed-by: Cédric Le Goater
Reviewed-by: Harsh Prateek Bora
---
v2: Bit-masks specified using PPC_BITMASK macro.
hw/pci-host
Add new XSCOM registers introduced in PHB5.
Apply bit-masks within xscom-write methods.
Signed-off-by: Saif Abrar
---
hw/pci-host/pnv_phb4.c | 29 +++--
hw/pci-host/pnv_phb4_pec.c | 33 -
include/hw/pci-host/pnv_phb4.h
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Signed-off-by: Saif Abrar
---
target/ppc/gdbstub.c |
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