[Qemu-devel] [PATCH v2 3/3] cpu-exec: elide more icount code if CONFIG_USER_ONLY

From: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> [Alex Bennée: #ifndef replay code to match elided functions] Signed-off-by: Alex Bennée <alex.ben...@linaro.org> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- cp

[Qemu-devel] [PATCH v2 0/3] tcg: Misc clean-up patches from Paolo and Alex

From: Sergey Fedorov <serge.f...@gmail.com> This patch series consists of various general TCG clean-up patches extracted from Paolo's MTTCG tree [1] and Alex's MTTCG base enablement tree [2]. The idea is to review and merge these patches separately from the MTTCG series to cut the latter an

[Qemu-devel] [PATCH v2 1/3] tcg: code_bitmap is not used by user-mode emulation

From: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> [Sergey Fedorov: eliminate the field entirely in user-mode] Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- Notes: Changes in v2: * The field is eliminated ent

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 29/03/16 19:26, Peter Maydell wrote: > On 29 March 2016 at 09:31, Sergey Fedorov <serge.f...@gmail.com> wrote: >> On 29/03/16 01:12, Richard Henderson wrote: >>> On 03/24/2016 08:11 AM, Paolo Bonzini wrote: >>>> There is also a case where a TB ju

Re: [Qemu-devel] [PATCH 2/5] tcg: reorganize tb_find_physical loop

On 29/03/16 17:26, Alex Bennée wrote: >> Alex, could you give your s-o-b for your variant of code? Or would you >> > like to make a patch by yourself? > Sure here: > > Signed-off-by: Alex Bennée > So I'm going to respin the series quickly dropping the last two contentious

Re: [Qemu-devel] [PATCH 2/5] tcg: reorganize tb_find_physical loop

On 29/03/16 16:26, Paolo Bonzini wrote: > > On 29/03/2016 15:19, Sergey Fedorov wrote: >> On 22/03/16 17:59, Alex Bennée wrote: >>> sergey.fedo...@linaro.org writes: >>> >>>> From: Paolo Bonzini <pbonz...@redhat.com> >>>> >>>>

Re: [Qemu-devel] [PATCH 2/5] tcg: reorganize tb_find_physical loop

On 22/03/16 17:59, Alex Bennée wrote: > sergey.fedo...@linaro.org writes: > >> From: Paolo Bonzini <pbonz...@redhat.com> >> >> Use a continue statement. >> >> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> >> [Sergey Fedorov: Fix moving t

Re: [Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

On 29/03/16 13:37, Paolo Bonzini wrote: > cpu_exec_nocache is not used in user-mode emulation, so it's okay if > qemu.git doesn't take the lock yet. (This kind of misunderstanding > about which code is thread-safe is going to be common until we have > MTTCG. This was the reason for the patch

Re: [Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

On 29/03/16 00:21, Paolo Bonzini wrote: > > On 28/03/2016 17:18, Sergey Fedorov wrote: >> The use pattern of 'tb_invalidated_flag' is a bit intricate; correct me, >> if I'm wrong about the following. Basically, 'tb_invalidated_flag' was >> meant to catch two events

Re: [Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 29/03/16 01:12, Richard Henderson wrote: > On 03/24/2016 08:11 AM, Paolo Bonzini wrote: >> There is also a case where a TB jumps to itself; it then appears twice >> in the list with different values in the low bits, such as this: >> >> tb->jmp_list_first = tb | 0; >>

Re: [Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

On 17/03/16 16:46, sergey.fedo...@linaro.org wrote: > First the translation block is invalidated, for which a simple write > to tb->pc is enough. This means that cpu-exec will not pick up anymore > the block, though it may still execute it through chained jumps. This > also replaces the NULLing

Re: [Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

On 17/03/16 18:14, Sergey Fedorov wrote: > On 17/03/16 18:09, Paolo Bonzini wrote: >> >> On 17/03/2016 14:46, sergey.fedo...@linaro.org wrote: >>> void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t >>> page_addr) >>> { >>> -CPUSt

[Qemu-devel] [PATCH v2 5/8] tcg: Clarify thread safety check in tb_add_jump()

From: Sergey Fedorov <serge.f...@gmail.com> The check is to make sure that another thread hasn't already done the same while we were outside of tb_lock. Mention this in a comment. Signed-off-by: Sergey Fedorov <serge.f...@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fed

[Qemu-devel] [PATCH v2 8/8] tcg: Clean up tb_jmp_unlink()

From: Sergey Fedorov <serge.f...@gmail.com> Unify the code of this function with tb_jmp_remove_from_list(). Making these functions similar improves their readability. Also this could be a step towards making this function thread-safe. Signed-off-by: Sergey Fedorov <serge.f...@gmail.co

[Qemu-devel] [PATCH v2 4/8] tcg: Init TB's direct jumps before making it visible

From: Sergey Fedorov <serge.f...@gmail.com> Initialize TB's direct jump list data fields and reset the jumps before tb_link_page() puts it into the physical hash table and the physical page list. So TB is completely initialized before it becomes visible. Signed-off-by: Sergey Fedorov &l

[Qemu-devel] [PATCH v2 7/8] tcg: Extract removing of jumps to TB from tb_phys_invalidate()

From: Sergey Fedorov <serge.f...@gmail.com> Move the code for removing jumps to a TB out of tb_phys_invalidate() to a separate static inline function tb_jmp_unlink(). This simplifies tb_phys_invalidate() and improves code structure. Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>

[Qemu-devel] [PATCH v2 3/8] tcg: Rearrange tb_link_page() to avoid forward declaration

From: Sergey Fedorov <serge.f...@gmail.com> Signed-off-by: Sergey Fedorov <serge.f...@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> Reviewed-by: Alex Bennée <alex.ben...@linaro.org> --- translate-all.c | 204

[Qemu-devel] [PATCH v2 0/8] tcg: Direct block chaining clean-up

From: Sergey Fedorov <serge.f...@gmail.com> This series combines a set of patches which is meant to improve overall code structure and readability of direct block chaining mechanism. The other point is to make a step towards thread safety of TB chainig. The series' tree can be found in a

[Qemu-devel] [PATCH v2 6/8] tcg: Rename tb_jmp_remove() to tb_remove_from_jmp_list()

From: Sergey Fedorov <serge.f...@gmail.com> tb_jmp_remove() was only used to remove the TB from a list of all TBs jumping to the same TB which is n-th jump destination of the given TB. Put a comment briefly describing the function behavior and rename it to better reflect its purpose. Sign

[Qemu-devel] [PATCH v2 2/8] tcg: Use uintptr_t type for jmp_list_{next|first} fields of TB

From: Sergey Fedorov <serge.f...@gmail.com> These fields do not contain pure pointers to a TranslationBlock structure. So uintptr_t is the most appropriate type for them. Also put an assert to assure that the two least significant bits of the pointer are zero before assigning it to jmp_list

[Qemu-devel] [PATCH v2 1/8] tcg: Clean up direct block chaining data fields

From: Sergey Fedorov <serge.f...@gmail.com> Briefly describe in a comment how direct block chaining is done. It should help in understanding of the following data fields. Rename some fields in TranslationBlock and TCGContext structures to better reflect their purpose (dropping excessiv

Re: [Qemu-devel] [PATCH v2 4/5] ./configure: accept stems to match a range of targets

24 марта 2016 г. 19:20 "Alex Bennée" <alex.ben...@linaro.org>: > Sergey Fedorov <serge.f...@gmail.com> writes: > > On 24/03/16 19:05, Alex Bennée wrote: > >> Sergey Fedorov <serge.f...@gmail.com> writes: > >> > >>> On 24/03/16 15

Re: [Qemu-devel] [PATCH 4/8] tcg: Init TB's direct jumps before making it visible

On 24/03/16 18:40, Alex Bennée wrote: > Sergey Fedorov <serge.f...@gmail.com> writes: > >> On 24/03/16 18:11, Alex Bennée wrote: >>> sergey.fedo...@linaro.org writes: >>>> From: Sergey Fedorov <serge.f...@gmail.com> >>>> >>>> d

Re: [Qemu-devel] [PATCH v2 4/5] ./configure: accept stems to match a range of targets

On 24/03/16 19:05, Alex Bennée wrote: > Sergey Fedorov <serge.f...@gmail.com> writes: > >> On 24/03/16 15:05, Alex Bennée wrote: >>> Sergey Fedorov <serge.f...@gmail.com> writes: >>> >>>> On 23/03/16 20:20, Alex Bennée wrote: >>>>

Re: [Qemu-devel] [PATCH 4/8] tcg: Init TB's direct jumps before making it visible

On 24/03/16 18:11, Alex Bennée wrote: > sergey.fedo...@linaro.org writes: >> From: Sergey Fedorov <serge.f...@gmail.com> >> >> diff --git a/translate-all.c b/translate-all.c >> index ca01dd325b8d..f68716e1819f 100644 >> --- a/translate-all.c >>

Re: [Qemu-devel] [PATCH 8/8] tcg: Clean up tb_jmp_unlink()

On 24/03/16 18:42, Sergey Fedorov wrote: > On 24/03/16 18:36, Alex Bennée wrote: >>> diff --git a/translate-all.c b/translate-all.c >>>> index 8b4bfa713bf7..56c77a72773d 100644 >>>> --- a/translate-all.c >>>> +++ b/translate-all.c >>>

Re: [Qemu-devel] [PATCH 2/8] tcg: Use uintptr_t type for jmp_list_{next|first} fields of TB

On 24/03/16 17:58, Alex Bennée wrote: >> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h >> > index cc3d2ca25917..cd96219a89e7 100644 >> > --- a/include/exec/exec-all.h >> > +++ b/include/exec/exec-all.h >> > @@ -275,14 +275,15 @@ struct TranslationBlock { >> > *

Re: [Qemu-devel] [PATCH 8/8] tcg: Clean up tb_jmp_unlink()

On 24/03/16 18:36, Alex Bennée wrote: >> diff --git a/translate-all.c b/translate-all.c >> > index 8b4bfa713bf7..56c77a72773d 100644 >> > --- a/translate-all.c >> > +++ b/translate-all.c >> > @@ -962,25 +962,21 @@ static inline void tb_reset_jump(TranslationBlock >> > *tb, int n) >> > /* remove

Re: [Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 24/03/16 16:42, Alex Bennée wrote: >> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h >> > index 05a151da4a54..cc3d2ca25917 100644 >> > --- a/include/exec/exec-all.h >> > +++ b/include/exec/exec-all.h >> > @@ -257,20 +257,32 @@ struct TranslationBlock { >> > struct

Re: [Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

On 24/03/16 18:01, Alex Bennée wrote: > Sergey Fedorov <serge.f...@gmail.com> writes: > >> On 24/03/16 16:42, Alex Bennée wrote: >>>> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h >>>>> index 05a151da4a54..cc3d2ca25917 100644 >>&g

Re: [Qemu-devel] [PATCH 2/8] tcg: Use uintptr_t type for jmp_list_{next|first} fields of TB

On 24/03/16 13:39, sergey.fedo...@linaro.org wrote: > - * The two least significant bits of a pointer are used to choose which > - * data field holds a pointer to the next TB: > + * jmp_list_first and jmp_list_next are 4-byte aligned pointers to a > + * TranslationBlock structure,

Re: [Qemu-devel] [PATCH 5/8] tcg: Clarify "thread safaty" check in tb_add_jump()

On 24/03/16 14:31, Paolo Bonzini wrote: > On 24/03/2016 11:39, sergey.fedo...@linaro.org wrote: >> +/* FIXME: This test provides only some probablistic "thread safety" for >> + * user-mode emulation; appropriate synchronization/locking scheme >> should >> + * be implemented. >> +

Re: [Qemu-devel] [PATCH 5/8] tcg: Clarify "thread safaty" check in tb_add_jump()

On 24/03/16 15:23, Artyom Tarasenko wrote: > s/safaty/safety/ ? Oops, silly typo :) Thanks, Sergey

Re: [Qemu-devel] [PATCH v2 4/5] ./configure: accept stems to match a range of targets

On 24/03/16 15:05, Alex Bennée wrote: > Sergey Fedorov <serge.f...@gmail.com> writes: > >> On 23/03/16 20:20, Alex Bennée wrote: >>> diff --git a/configure b/configure >>> index b88d0db..ebf8a42 100755 >>> --- a/configure >>> +++

[Qemu-devel] tcg/ppc: maintainer's mail delivery failure

3:39:41 -0700 (PDT) From: sergey.fedo...@linaro.org To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.ben...@linaro.org>, Sergey Fedorov <serge.f...@gmail.com>, Paolo Bonzini <pbonz...@redhat.com>, Peter Crosthwaite <crosthwaite.pe...@g

[Qemu-devel] [PATCH 8/8] tcg: Clean up tb_jmp_unlink()

From: Sergey Fedorov <serge.f...@gmail.com> Unify the code of this function with tb_jmp_remove_from_list(). Making these functions similar improves their readability. Also this could be a step towards making this function thread-safe. Signed-off-by: Sergey Fedorov <serge.f...@gmail.co

[Qemu-devel] [PATCH 3/8] tcg: Rearrange tb_link_page() to avoid forward declaration

From: Sergey Fedorov <serge.f...@gmail.com> Signed-off-by: Sergey Fedorov <serge.f...@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- translate-all.c | 204 1 file changed, 101 insertions(+), 103

[Qemu-devel] [PATCH 4/8] tcg: Init TB's direct jumps before making it visible

From: Sergey Fedorov <serge.f...@gmail.com> Initialize TB's direct jump list data fields and reset the jumps before tb_link_page() puts it into the physical hash table and the physical page list. So TB is completely initialized before it becomes visible. Signed-off-by: Sergey Fedorov &l

[Qemu-devel] [PATCH 2/8] tcg: Use uintptr_t type for jmp_list_{next|first} fields of TB

From: Sergey Fedorov <serge.f...@gmail.com> These fields do not contain pure pointers to a TranslationBlock structure. So uintptr_t is the most appropriate type for them. Also put an assert to assure that the two least significant bits of the pointer are zero before assigning it to jmp_list

[Qemu-devel] [PATCH 5/8] tcg: Clarify "thread safaty" check in tb_add_jump()

From: Sergey Fedorov <serge.f...@gmail.com> The check does not give an absolute guarantee of thread safety because there still may be a race condition between two threads which both have just read zero from jmp_list_next[n] and proceed with list modification. Clarify this in the c

[Qemu-devel] [PATCH 7/8] tcg: Extract removing of jumps to TB from tb_phys_invalidate()

From: Sergey Fedorov <serge.f...@gmail.com> Move the code for removing jumps to a TB out of tb_phys_invalidate() to a separate static inline function tb_jmp_unlink(). This simplifies tb_phys_invalidate() and improves code structure. Signed-off-by: Sergey Fedorov <serge.f...@gmail.com>

[Qemu-devel] [PATCH 6/8] tcg: Rename tb_jmp_remove() to tb_remove_from_jmp_list()

From: Sergey Fedorov <serge.f...@gmail.com> tb_jmp_remove() was only used to remove the TB from a list of all TBs jumping to the same TB which is n-th jump destination of the given TB. Put a comment briefly describing the function behavior and rename it to better reflect its purpose. Sign

[Qemu-devel] [PATCH 1/8] tcg: Clean up direct block chaining data fields

From: Sergey Fedorov <serge.f...@gmail.com> Briefly describe in a comment how direct block chaining is done. It should help in understanding of the following data fields. Rename some fields in TranslationBlock and TCGContext structures to better reflect their purpose (dropping excessiv

[Qemu-devel] [PATCH 0/8] tcg: Direct block chaining clean-up

From: Sergey Fedorov <serge.f...@gmail.com> This series combines a set of patches which is meant to improve overall code structure and readability of direct block chaining mechanism. The other point is to make a step towards thread safety of TB chainig. The series' tree can be found in a

Re: [Qemu-devel] [PATCH v2 4/5] ./configure: accept stems to match a range of targets

On 23/03/16 20:20, Alex Bennée wrote: > diff --git a/configure b/configure > index b88d0db..ebf8a42 100755 > --- a/configure > +++ b/configure > @@ -1246,7 +1246,8 @@ Standard options: >--target-list=LIST set target list (default: build everything) > $(echo Available targets:

Re: [Qemu-devel] [PATCH v7 4/4] arm: implement query-gic-capabilities

redhat.com> Acked-by: Sergey Fedorov <serge.f...@gmail.com> Kind regards, Sergey > --- > target-arm/monitor.c | 58 > +++- > 1 file changed, 57 insertions(+), 1 deletion(-) > > diff --git a/target-arm/monitor.c b/target-

Re: [Qemu-devel] [PATCH v7 3/4] kvm: add kvm_device_supported() helper function

On 24/03/16 05:55, Peter Xu wrote: > This can be used when probing whether KVM support specific device. Here, > a raw vmfd is used. > > Signed-off-by: Peter Xu <pet...@redhat.com> Acked-by: Sergey Fedorov <serge.f...@gmail.com> Kind regards, Sergey > --- &

Re: [Qemu-devel] [PATCH v7 2/4] arm: enhance kvm_arm_create_scratch_host_vcpu

On 24/03/16 05:55, Peter Xu wrote: > Some more lines to make sure we allow NULL for 1st/3rd parameter. > > Signed-off-by: Peter Xu <pet...@redhat.com> Acked-by: Sergey Fedorov <serge.f...@gmail.com> Kind regards, Sergey > --- > target-arm/kvm.c | 14 +++

Re: [Qemu-devel] [PATCH v6 3/4] kvm: add kvm_support_device() helper function

On 23/03/16 17:56, Peter Xu wrote: > On Wed, Mar 23, 2016 at 03:28:28PM +0300, Sergey Fedorov wrote: >> On 23/03/16 08:32, Peter Xu wrote: >>> diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h >>> index 6695fa7..8738fa1 100644 >>> --- a/include/sysemu/

Re: [Qemu-devel] [Qemu-arm] [PATCH v6 4/4] arm: implement query-gic-capabilities

On 23/03/16 08:32, Peter Xu wrote: > diff --git a/target-arm/monitor.c b/target-arm/monitor.c > index 254a9c9..4a2db59 100644 > --- a/target-arm/monitor.c > +++ b/target-arm/monitor.c > @@ -21,8 +21,66 @@ (snip) > GICCapabilityResult *qmp_query_gic_capabilities(Error **errp) > { > -return

Re: [Qemu-devel] [PATCH v6 3/4] kvm: add kvm_support_device() helper function

On 23/03/16 08:32, Peter Xu wrote: > diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h > index 6695fa7..8738fa1 100644 > --- a/include/sysemu/kvm.h > +++ b/include/sysemu/kvm.h > @@ -306,6 +306,15 @@ void kvm_device_access(int fd, int group, uint64_t attr, > */ > int

Re: [Qemu-devel] [Qemu-arm] [PATCH v6 2/4] arm: enhance kvm_arm_create_scratch_host_vcpu

On 23/03/16 08:32, Peter Xu wrote: > diff --git a/target-arm/kvm.c b/target-arm/kvm.c > index 969ab0b..0a7f9a6 100644 > --- a/target-arm/kvm.c > +++ b/target-arm/kvm.c > @@ -62,13 +62,17 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t > *cpus_to_try, > goto err; > } > > +

Re: [Qemu-devel] [PATCH 5/5] tcg: move tb_invalidated_flag to CPUState

On 22/03/16 18:07, Alex Bennée wrote: > sergey.fedo...@linaro.org writes: (snip) >> diff --git a/cpu-exec.c b/cpu-exec.c >> index f90482eff778..07545aa91082 100644 >> --- a/cpu-exec.c >> +++ b/cpu-exec.c >> @@ -195,10 +195,11 @@ static void cpu_exec_nocache(CPUState *cpu, int >> max_cycles, >>

[Qemu-devel] [PATCH 5/5] tcg: move tb_invalidated_flag to CPUState

From: Paolo Bonzini <pbonz...@redhat.com> This is a baby step towards making tb_flush thread safe. Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- cpu-exec.c | 11 +-- include/exec/exec-all.

[Qemu-devel] [PATCH 1/5] tcg: code_bitmap is not used by user-mode emulation

From: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- translate-all.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/translate-all.c b/tra

[Qemu-devel] [PATCH 2/5] tcg: reorganize tb_find_physical loop

From: Paolo Bonzini <pbonz...@redhat.com> Use a continue statement. Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> [Sergey Fedorov: Fix moving to list head in case of no TB] Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --

Re: [Qemu-devel] [PATCH 3/5] tcg: always keep jump target and tb->jmp_next consistent

On 17/03/16 23:46, Richard Henderson wrote: On 03/17/2016 01:45 PM, Sergey Fedorov wrote: Probably it's time to audit the code that handles direct jumping and clean-up/document/rename things to make it more easy to understand? :) Seconded! I'll go for it, then :) Kind regards, Sergey

Re: [Qemu-devel] [PATCH 1/5] tcg: code_bitmap is not used by user-mode emulation

On 17/03/16 17:56, Peter Maydell wrote: On 17 March 2016 at 13:46, <sergey.fedo...@linaro.org> wrote: From: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- translate

[Qemu-devel] [PATCH 3/5] tcg: always keep jump target and tb->jmp_next consistent

From: Paolo Bonzini <pbonz...@redhat.com> Simple code simplification. Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- translate-all.c | 19 +-- 1 file changed, 9 insertions(+), 10 deleti

Re: [Qemu-devel] [PATCH 3/5] tcg: always keep jump target and tb->jmp_next consistent

On 17/03/16 23:45, Sergey Fedorov wrote: On 17/03/16 22:31, Paolo Bonzini wrote: On 17/03/2016 18:57, Richard Henderson wrote: @@ -951,18 +959,10 @@ static inline void tb_jmp_remove(TranslationBlock *tb, int n) } /* now we can suppress tb(n) from the list

[Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

t for now, but it will be the right order when tb_find_fast is moved outside the tb_lock. Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> Signed-off-by: Sergey Fedorov <sergey.fedo...@linaro.org> --- translate-all.c | 56 1 file changed,

[Qemu-devel] [PATCH 0/5] tcg: Misc clean-up patches from Paolo

From: Sergey Fedorov <sergey.fedo...@linaro.org> This patch series consists of various general TCG clean-up patches extracted from Paolo's MTTCG tree [1]. The idea is to review and merge these patches separately from the MTTCG series to cut the latter and make it easier to review. [1]

Re: [Qemu-devel] [PATCH 3/5] tcg: always keep jump target and tb->jmp_next consistent

On 17/03/16 22:31, Paolo Bonzini wrote: On 17/03/2016 18:57, Richard Henderson wrote: @@ -951,18 +959,10 @@ static inline void tb_jmp_remove(TranslationBlock *tb, int n) } /* now we can suppress tb(n) from the list */ *ptb = tb->jmp_next[n]; - -

Re: [Qemu-devel] [PATCH 4/5] tcg: reorder removal from lists in tb_phys_invalidate

On 17/03/16 18:09, Paolo Bonzini wrote: On 17/03/2016 14:46, sergey.fedo...@linaro.org wrote: void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) { -CPUState *cpu; PageDesc *p; unsigned int h, n1; +tb_page_addr_t pc; tb_page_addr_t phys_pc;

Re: [Qemu-devel] [Qemu-arm] [PATCH] Fix bug: SRS instructions would trap to EL3 in Secure EL1 even if specified mode was not monitor mode.

On 07.03.2016 00:14, Peter Maydell wrote: On 7 March 2016 at 02:04, Sergey Fedorov <serge.f...@gmail.com> wrote: On 23.02.2016 01:25, Ralf-Philipp Weinmann wrote: According to the ARMv8 Architecture reference manual [F6.1.203], ALL of the following conditions need to be met for SRS t

Re: [Qemu-devel] [Qemu-arm] [PATCH] Fix bug: SRS instructions would trap to EL3 in Secure EL1 even if specified mode was not monitor mode.

On 23.02.2016 01:25, Ralf-Philipp Weinmann wrote: According to the ARMv8 Architecture reference manual [F6.1.203], ALL of the following conditions need to be met for SRS to trap to EL3: * It is executed at Secure PL1. * The specified mode is monitor mode. * EL3 is using AArch64. The code

Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Fix translation level on early translation faults

On 03.03.2016 17:55, Peter Maydell wrote: > On 3 March 2016 at 14:48, Sergey Fedorov <serge.f...@gmail.com> wrote: >> On 03.03.2016 16:49, Peter Maydell wrote: >>> On 2 March 2016 at 19:19, Sergey Fedorov <serge.f...@gmail.com> wrote: >>>> On 02.03.20

Re: [Qemu-devel] [PATCH] target-arm: Fix translation level on early translation faults

On 03.03.2016 16:49, Peter Maydell wrote: > On 2 March 2016 at 19:19, Sergey Fedorov <serge.f...@gmail.com> wrote: >> On 02.03.2016 21:04, Sergey Sorokin wrote: >>> Qemu reports translation fault on 1st level instead of 0th level in case of >>> AArch64 address tra

Re: [Qemu-devel] [PATCH] target-arm: Fix translation level on early translation faults

On 02.03.2016 21:04, Sergey Sorokin wrote: Qemu reports translation fault on 1st level instead of 0th level in case of AArch64 address translation if the translation table walk is disabled or the address is in the gap between the two regions. Signed-off-by: Sergey Sorokin

Re: [Qemu-devel] [PATCH] target-arm: Fix translation level on early translation faults

On 02.03.2016 21:04, Sergey Sorokin wrote: > Qemu reports translation fault on 1st level instead of 0th level in case of > AArch64 address translation if the translation table walk is disabled or > the address is in the gap between the two regions. It's probably not a very clear description in

Re: [Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

use there is no way to set the interrupt group to 1, if gic_has_groups() is not true. Anyway, Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> + +if (!gic_eoi_split(s, cpu, attrs)) { +/* This is UNPREDICTABLE; we choose to ignore it */ +qemu_log_mask(LOG_GUEST_E

Re: [Qemu-devel] [PATCH] target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode

t; Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> --- target-arm/helper.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 18c8296..935f13b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5490

Re: [Qemu-devel] [PATCH] target-arm: Implement MRS (banked) and MSR (banked) instructions

On 29.02.2016 19:18, Peter Maydell wrote: > Starting with the ARMv7 Virtualization Extensions, the A32 and T32 > instruction sets provide instructions "MSR (banked)" and "MRS > (banked)" which can be used to access registers for a mode other > than the current one: > * R_ > * ELR_hyp > * SPSR_

Re: [Qemu-devel] [PATCH v2 4/8] target-arm: Add more fields to the data abort syndrome generator

On 25.02.2016 20:41, Peter Maydell wrote: On 19 February 2016 at 20:04, Edgar E. Iglesias wrote: From: "Edgar E. Iglesias" Add the following flags to the data abort syndrome generator: * isv - Instruction syndrome valid * sas - Syndrome

Re: [Qemu-devel] [PATCH v2 2/2] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps

> also need a new access function which only implements the > TPM checks for use by the few not-EL0-accessible registers > and by PMUSERENR_EL0 (which is always EL0-readable). > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.

Re: [Qemu-devel] [PATCH v2 1/2] target-arm: Fix handling of SDCR for 32-bit code

uint64_t value) > +{ > +env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; > +} > + Just one comment. As soon as we cannot have both of MDCR_EL3 in SDCR in a specific CPU configuration (EL3 is either AArch64 or AArch32), the RES0 bitfields of SDCR are "RES0 in all contexts".

Re: [Qemu-devel] [PATCH] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps

On 19.02.2016 14:26, Peter Maydell wrote: > Implement the performance monitor register traps controlled > by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance > registers already have an access function to deal with the > user-enable bit, and the TPM checks can be added there. We > also need

Re: [Qemu-devel] [PATCH 09/11] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL

en to as normal > > This is pretty much the same behaviour we picked for our > UNPREDICTABLE handling, with the exception that for v8 we > need to set the IL bit. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gma

Re: [Qemu-devel] [PATCH 11/11] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1

ck from the v8 ARM ARM G1.9.3 and so it's worth adding now; the > rest of the HCR.TGE checks can be added later as necessary.) > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/helper.c | 1

Re: [Qemu-devel] [PATCH 08/11] target-arm: Forbid mode switch to Mon from Secure EL1

s 3, > which then gives the correct answer whether EL3 is AArch32 > or AArch64. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 delet

Re: [Qemu-devel] [PATCH 10/11] target-arm: Make mode switches from Hyp via CPS and MRS illegal

ell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/helper.c | 12 ++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 69e93a2..e1af9d5 100644 &

Re: [Qemu-devel] [PATCH 07/11] target-arm: Add Hyp mode checks to bad_mode_switch()

On 15.02.2016 20:22, Peter Maydell wrote: > We don't actually support Hyp mode yet, but add the correct > checks for it to the bad_mode_switch() function for completeness. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <

Re: [Qemu-devel] [PATCH 05/11] target-arm: In cpsr_write() ignore mode switches from User mode

mply ignored (and not > treated as a bad mode switch, which in v8 sets CPSR.IL). Make > mode switches from User ignored in cpsr_write() as well, for > consistency. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.co

Re: [Qemu-devel] [PATCH 06/11] target-arm: Add comment about not implementing NSACR.RFR

CPU's Secure state. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c >

Re: [Qemu-devel] [PATCH 04/11] linux-user: Use restrictive mask when calling cpsr_write()

mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > linux-user/main.c | 3 ++- > linux-user/signal.c | 2 +- > 2 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/linux-user/main.c b/linux-user/main.c > index 1269470..c467fa7 100

Re: [Qemu-devel] [PATCH 03/11] target-arm: Raw CPSR writes should skip checks and bank switching

the register state if the mode from the last exit to userspace > differed from the mode on this exit. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/helper.c| 5 +++-- > target-arm/

Re: [Qemu-devel] [PATCH 02/11] target-arm: Add write_type argument to cpsr_write()

On 15.02.2016 20:22, Peter Maydell wrote: > Add an argument to cpsr_write() to indicate what kind of CPSR > write is being requested, since the exact behaviour should > differ for the different cases. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Se

Re: [Qemu-devel] [PATCH 01/11] target-arm: Give CPSR setting on 32-bit exception return its own helper

CPS.) Split the exception-return case into > its own helper for setting CPSR, so we can eventually handle them > differently in the helper function. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- >

Re: [Qemu-devel] [PATCH v1 6/9] target-arm/translate-a64.c: Unify some of the ldst_reg decoding

ding in preparation for generating > instruction syndromes for data aborts. > This will allow us to reduce the number of places to hook in updates > to the load/store state needed to generate the insn syndromes. > > No functional change. > > Signed-off-by: Edgar E. Iglesias <edgar.

Re: [Qemu-devel] [PATCH v1 5/9] target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9

iants. > > No functional change. > > Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/translate-a64.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff -

Re: [Qemu-devel] [PATCH v1 3/9] target-arm: Add the thumb/IL flag to syn_data_abort

On 12.02.2016 17:33, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/internals.h | 4 +++- > target-arm/op_helper.c | 6 -- > 2 files changed, 7 insertions(+), 3 deletions(-) >

Re: [Qemu-devel] [PATCH 2/4] target-arm: Move get/set_r13_banked() to op_helper.c

n for the helper.c/op_helper.c split was that > only op_helper.c had access to the CPU env pointer; this distinction > has not been true for a long time, though, and so the split is > now rather arbitrary.) > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-b

Re: [Qemu-devel] [PATCH 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case

gned-off-by: Peter Maydell <peter.mayd...@linaro.org> It's a bit misleading that the name "get_r13_banked" says nothing about SRS instruction but raises an SRS-specific exception. Though, it's only used for SRS and there seems to be no other candidate to use it; so Reviewed-by: Se

Re: [Qemu-devel] [PATCH 3/4] target-arm: Combine user-only and softmmu get/set_r13_banked()

s that can't compile in > CONFIG_USER_ONLY, so combine the two functions rather than > having completely split versions under ifdefs. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > target-arm/op_helper.

Re: [Qemu-devel] [PATCH 1/4] target-arm: Clean up trap/undef handling of SRS

gt; > The exception is that we don't UNDEF for calls from System > mode, which need a runtime check. This will be dealt with in > the following commits. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <

Re: [Qemu-devel] [PATCH] target-arm: Move bank_number() into internals.h

On 12.02.2016 18:50, Peter Maydell wrote: > Move bank_number()'s implementation into internals.h, so > it's available in the user-mode-only compile as well. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> >

Re: [Qemu-devel] [PATCH 3/4] target-arm: Combine user-only and softmmu get/set_r13_banked()

t;> Do we really need the assert? >>> If we keep it, can't we have it for both -user and -softmmu (avoiding the >>> ifdef)? >> I would be happy to entirely drop the assert, yes. > OK, thanks. > > With that change: > Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > Yes, I also think it would be okay to drop that assert. Anyway: Reviewed-by: Sergey Fedorov <serge.f...@gmail.com>

Re: [Qemu-devel] [PATCH v2 1/6] target-arm: correct CNTFRQ access rights

e code, provide a new utility function > arm_highest_el() which returns the highest implemented > exception level. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > Rewritten to use arm_highest_el() t

Re: [Qemu-devel] [Qemu-arm] [PATCH 2/6] target-arm: Fix handling of SCR.SMD

on, and clarify the comment both to reflect this and > to expand slightly on what's going on for the v7-no-Virtualization case. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Sergey Fedorov <serge.f...@gmail.com> > --- > The bit about forcing SMD

Re: [Qemu-devel] [PATCH 5/6] target-arm: Implement MDCR_EL2.TDA and MDCR_EL2.TDA traps

One of the MDCR_EL2's should be MDCR_EL3 instead. On 05.02.2016 19:45, Peter Maydell wrote: > Implement the debug register traps controlled by MDCR_EL2.TDA > and MDCR_EL3.TDA. > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 39

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