One of the MDCR_EL2's should be MDCR_EL3 instead.
On 05.02.2016 19:45, Peter Maydell wrote:
> Implement the debug register traps controlled by MDCR_EL2.TDA
> and MDCR_EL3.TDA.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper.c | 39 ++-
> 1 file chan
On 05.02.2016 19:45, Peter Maydell wrote:
> Implement the traps to EL2 and EL3 controlled by the bits
> MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap
> accesses to the "powerdown debug" registers.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedo
On 05.02.2016 19:45, Peter Maydell wrote:
> Implement trapping of the "debug ROM" registers, which are controlled
> by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
&g
tion, and clarify the comment both to reflect this and
> to expand slightly on what's going on for the v7-no-Virtualization case.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> The bit about forcing SMD to zero confused me, anyway, since
On 05.02.2016 19:44, Peter Maydell wrote:
> Correct some corner cases we were getting wrong for
> CNTFRQ access rights:
> * should UNDEF from 32-bit Secure EL1
> * only writable from the highest implemented exception level,
>which might not be EL1 now
>
> Signed-off-by: Peter Maydell
> ---
>
n falls over because it
> doesn't have a UEFI image it can chain to).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> target-arm/cpu64.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index
eing checked
> is a read or a write.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> target-arm/cpu.h | 4 ++-
> target-arm/helper.c| 81
> +-
> target-arm/helper.h| 2 +
On 03.02.2016 16:38, Peter Maydell wrote:
> The arm_generate_debug_exceptions() function as originally implemented
> assumes no EL2 or EL3. Since we now have much more of an implementation
> of those now, fix this assumption.
>
> Signed-off-by: Peter Maydell
Reviewed-by:
On 03.02.2016 16:38, Peter Maydell wrote:
> Implement the MDCR_EL3 register (which is SDCR for AArch32).
> For the moment we implement it as reads-as-written.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/cpu.h| 1 +
> target-arm/helper.c | 24
> 2 files change
gned-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> target-arm/translate.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 10792e8..fa8e22c 100644
> --- a/target-arm/translate.c
>
gned-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> target-arm/translate.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 3ec758a..10792e8 100644
> --- a/target-arm/translate
7; instead.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> target-arm/internals.h | 28 ++--
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target-arm/internals.h b/target-arm/internals.h
> index d226b
On 03.02.2016 16:38, Peter Maydell wrote:
> Fix a typo where "EL2" was written but "EL3" intended.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> target-arm/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
real world guest code running at EL3
> (trusted firmware or bootloaders) will query the ID registers to
> determine whether it should start a guest Linux kernel in EL2 or EL3.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> When full EL2 arrives and we have
dedicated watchpoint checking callback.
Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Maydell
---
target-arm/cpu.c | 1 +
target-arm/internals.h | 3 +++
target-arm/op_helper.c | 35 +--
3 files changed, 25 insertions(+), 14 deletions(-)
diff --git a
raising a TCG exception.
Signed-off-by: Sergey Fedorov
---
exec.c| 6 ++
include/qom/cpu.h | 4
qom/cpu.c | 9 +
3 files changed, 19 insertions(+)
diff --git a/exec.c b/exec.c
index 9e076bc..14e7c76 100644
--- a/exec.c
+++ b/exec.c
@@ -2024,6 +2024,7 @@ static
ing checked passed to debug_check_watchpoint()
callback
* BP_WATCHPOINT_HIT flag cleared from flags from wp->flags in no-fire case
* Comment for debug_check_watchpoint() callback improved
Sergey Fedorov (2):
cpu: Add callback to check architectural watchpoint match
target-arm: Imp
On 29.01.2016 22:17, Sergey Fedorov wrote:
> This series is intended to fix ARM watchpoint emulation misbehavior.
> QEMU hangs when QEMU watchpoint fires but it does not pass additional
> architectural checks in ARM CPU debug exception handler. For details,
> please see individual
dedicated watchpoint checking callback.
Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Maydell
---
target-arm/cpu.c | 1 +
target-arm/internals.h | 3 +++
target-arm/op_helper.c | 35 +--
3 files changed, 25 insertions(+), 14 deletions(-)
diff --git a
ing checked passed to debug_check_watchpoint()
callback
* Comment for debug_check_watchpoint() callback improved
Sergey Fedorov (2):
cpu: Add callback to check architectural watchpoint match
target-arm: Implement checking of fired watchpoint
exec.c | 5 +
include/
raising a TCG exception.
Signed-off-by: Sergey Fedorov
---
Notes:
Changes in v2:
* Check moved before setting cpu->watchpoint_hit
* Pointer to watchpoint being checked passed to debug_check_watchpoint()
callback
* Comment for debug_check_watchpoint() callback improved
exe
On 29.01.2016 20:05, Peter Maydell wrote:
> On 29 January 2016 at 16:45, Sergey Fedorov wrote:
>> > On 14.01.2016 21:34, Peter Maydell wrote:
>>> >> Support EL2 and EL3 in arm_el_is_aa64() by implementing the
>>> >> logic for checking the SCR_EL3
On 29.01.2016 19:45, Sergey Fedorov wrote:
> On 14.01.2016 21:34, Peter Maydell wrote:
>> > Support EL2 and EL3 in arm_el_is_aa64() by implementing the
>> > logic for checking the SCR_EL3 and HCR_EL2 register-width bits
>> > as appropriate to determine the reg
> We were only squashing bit 0; also squash bit 1 if the SPSR T bit
> indicates this is a return to ARM code.
Reviewed-by: Sergey Fedorov
> Signed-off-by: Peter Maydell
> ---
> target-arm/op_helper.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff
n to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1
>
> (We don't implement external debug, so the case of "debug state exit
> from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply
> for QEMU.)
Reviewed-by: Sergey Fedorov
>
> EL2 is not implemented.)
Reviewed-by: Sergey Fedorov
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper.c | 21 -
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d37c82c..19
rn to 64-bit.
Reviewed-by: Sergey Fedorov
> Signed-off-by: Peter Maydell
> ---
> target-arm/op_helper.c | 80
> +-
> 1 file changed, 59 insertions(+), 21 deletions(-)
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_
an entry to AArch32
> or AArch64. (EXCP_SEMIHOST is also an "internal exception" so
> it has no target exception level in the first place.)
>
> This will allow AArch32 EL1 code to use semihosting calls when
> running under an AArch64 EL3.
Reviewed-by: Sergey Fed
mihosting semantics depend on the register width
> of the calling code, not on that of any higher EL).
Reviewed-by: Sergey Fedorov
> Signed-off-by: Peter Maydell
> ---
> target-arm/cpu-qom.h | 2 --
> target-arm/cpu64.c | 3 ---
> target-arm/helper.c | 75
> ++
On 14.01.2016 21:34, Peter Maydell wrote:
> Move the aarch64_cpu_do_interrupt() function to helper.c. We want
> to be able to call this from code that isn't AArch64-only, and
> the move allows us to avoid awkward #ifdeffery at the callsite.
Reviewed-by: Sergey Fedorov
> Sig
On 14.01.2016 21:34, Peter Maydell wrote:
> Support EL2 and EL3 in arm_el_is_aa64() by implementing the
> logic for checking the SCR_EL3 and HCR_EL2 register-width bits
> as appropriate to determine the register width of lower exception
> levels.
Reviewed-by: Sergey Fedorov
>
EXC
>> register for a lower exception level that is using AArch32.
>>
>> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
>> ---
>> ARM Trusted Firmware expects this to exist (as does your average
>> hypervisor, I expect).
>>
>> target
ve them from el2_cp_reginfo[] to
> v8_cp_reginfo[] so they are always present.
Reviewed-by: Sergey Fedorov
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/helper.c | 58
> ++---
> 1 file changed, 29 insertions(+), 29 del
On 12/16/15 20:03, Richard Henderson wrote:
On 12/15/2015 01:02 PM, Sergey Fedorov wrote:
For that, I think it might be interesting to arrange for non-empty
TBs to
exit prior to recognizing a breakpoint. So that a breakpoint TB is
always
just the one operation. Except for the fact that
On 12/14/15 19:19, Richard Henderson wrote:
On 12/12/2015 12:02 PM, Sergey Fedorov wrote:
On 12/12/15 02:39, Richard Henderson wrote:
On 12/10/2015 10:47 AM, Sergey Fedorov wrote:
The "PC advancement" trick was used just after recognizing that a
breakpoint exception was going to be
On 12/12/15 02:39, Richard Henderson wrote:
On 12/10/2015 10:47 AM, Sergey Fedorov wrote:
The "PC advancement" trick was used just after recognizing that a
breakpoint exception was going to be generated. This trick has had two
points:
1. Guarantee that tb->size isn't ze
On 11.12.2015 06:43, Valerón JC wrote:
> I want to trace a bug in tcg, which for me, at some point, generate
> infinite loop TB chains, that's unexpected. and I've found the final
> TB(head, since they're chaining) which run in an infinite loop, and I
> know a very weird trick to 'disable' this bug
hecking for TB size at the end of
translation. If we get an empty TB then just set tb->size to 1 and skip
disassembling. Setting tb->size to 1 is enough to get correct behaviour,
whereas an empty TB doesn't obviously need to be disassembled.
Suggested-by: Peter Maydell
Signed-off-by: S
On 26.11.2015 15:33, Peter Maydell wrote:
> On 25 November 2015 at 18:02, Sergey Fedorov wrote:
>> The AArch32 translation completion code for singlestep enabled/active
>> case was a way more confusing and too repetitive then it needs to be.
>> Probably that was the
is failed
- Write the condexec bits back to the CPU state
- Write the PC back to the CPU state since it hasn't been written in
this case
- Generate an appropriate singlestep exception
Signed-off-by: Sergey Fedorov
---
target-arm/translate.c | 65 ---
on-exclusive load-acquire/store-release
> pair". Delete that broken and now unreachable code.
>
> Reported-by: Laurent Desnogues
> Signed-off-by: Peter Maydell
Reviewed-by: Sergey Fedorov
> ---
> The easiest way to validate that we have the unallocated
> conditions c
On 24.11.2015 14:03, Peter Maydell wrote:
> On 23 November 2015 at 18:54, Sergey Fedorov wrote:
>> On 23.11.2015 21:42, Sergey Fedorov wrote:
>>> On 23.11.2015 19:49, Peter Maydell wrote:
>>>> Ping? I forgot to mark this for-2.5, and given how long the bug's
&
On 23.11.2015 21:42, Sergey Fedorov wrote:
> On 23.11.2015 19:49, Peter Maydell wrote:
>> Ping? I forgot to mark this for-2.5, and given how long the bug's
>> been hanging around there's not much urgency to fixing it, but
>> we might as well put the fix into 2.5 if i
On 23.11.2015 19:49, Peter Maydell wrote:
> Ping? I forgot to mark this for-2.5, and given how long the bug's
> been hanging around there's not much urgency to fixing it, but
> we might as well put the fix into 2.5 if it gets reviewed.
>
Hi, Peter. I'm going to review this carefully in a few days
On 17.11.2015 16:12, Sergey Smolov wrote:
>
> 03.11.2015 20:29, Peter Crosthwaite пишет:
>> On Tue, Nov 3, 2015 at 8:14 AM, Peter Maydell
>> wrote:
>>> On 3 November 2015 at 13:17, Sergey Smolov wrote:
I have a collection of ARMv8 register names. I need to add special
logging
mode
Architectural breakpoint check could raise an exceptions, thus condexec
bits should be updated before calling gen_helper_check_breakpoints().
Signed-off-by: Sergey Fedorov
---
target-arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/translate.c b/target-arm
Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.
Signed-off-by: Sergey Fedorov
---
Notes:
Changes in v2:
* Typo fixed
target-arm/translate.c | 1 +
1 file changed, 1
Changes in v2:
* Typo fixed in the first patch
Sergey Fedorov (2):
target-arm: Update condexec before CP access check in AA32 translation
target-arm: Update condexec before arch BP check in AA32 translation
target-arm/translate.c | 2 ++
1 file changed, 2 insertions(+)
--
1.9.1
On 17.11.2015 16:31, Peter Maydell wrote:
> On 17 November 2015 at 10:59, Sergey Fedorov wrote:
>> On 16.11.2015 22:34, Sergey Fedorov wrote:
>>> Coprocessor access instructions are allowed inside IT block.
>>> gen_helper_access_check_cp_reg() can raise an exceptions th
On 16.11.2015 22:34, Sergey Fedorov wrote:
> Coprocessor access instructions are allowed inside IT block.
> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
> bits should be updated before.
>
> Signed-off-by: Sergey Fedorov
> ---
> target-arm/transl
Sergey Fedorov (2):
target-arm: Update condexec before CP access check in AA32 translation
target-arm: Update condexec before arch BP check in AA32 translation
target-arm/translate.c | 2 ++
1 file changed, 2 insertions(+)
--
1.9.1
Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.
Signed-off-by: Sergey Fedorov
---
target-arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/translate.c
Architectural breakpoint check could raise an exceptions, thus condexec
bits should be updated before calling gen_helper_check_breakpoints().
Signed-off-by: Sergey Fedorov
---
target-arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/translate.c b/target-arm
On 14.11.2015 22:45, Peter Maydell wrote:
> On 13 November 2015 at 21:13, Sergey Fedorov wrote:
>> On 10.11.2015 15:15, Peter Maydell wrote:
>>> So the way the 32-bit code works for singlestep is complicated
>>> because of the need to handle the conditional instructions
On 10.11.2015 15:15, Peter Maydell wrote:
> So the way the 32-bit code works for singlestep is complicated
> because of the need to handle the conditional instructions,
> which means you get a lot more cases like "this is a conditional
> SWI" that need to be handled. A quick summary of some of the
PC should be updated in the CPU state before calling check_breakpoints()
helper. Otherwise, the helper would not see the correct PC in the CPU
state if it is not at the start of a TB.
Signed-off-by: Sergey Fedorov
---
target-arm/translate-a64.c | 1 +
target-arm/translate.c | 1 +
2 files
PC in CPU state and execution
hangs.
Signed-off-by: Sergey Fedorov
---
Though I don't clearly understand how singlestepping is done here, I just do
what Peter suggested in his commnets for v1 and send this patch for review. I'm
going to get into this while the patch is in review pr
On 06.11.2015 15:46, Peter Maydell wrote:
> On 2 November 2015 at 18:16, Sergey Fedorov wrote:
>> AArch32 translation code does not distinguish between DISAS_UPDATE and
>> DISAS_JUMP. Thus, we cannot use any of them without first updating PC in
>> CPU state. Furthermore, it
On 06.11.2015 14:57, Peter Maydell wrote:
> On 5 November 2015 at 12:26, Sergey Fedorov wrote:
>> Do not raise a CPU exception if no CPU breakpoint has fired, since
>> singlestep is also done by generating a debug internal exception. This
>> fixes a bug with sing
Do not raise a CPU exception if no CPU breakpoint has fired, since
singlestep is also done by generating a debug internal exception. This
fixes a bug with singlestepping in gdbstub.
Signed-off-by: Sergey Fedorov
---
This is a v2 of 'target-arm: Fix arm_debug_excp_handler() for singlestep
en
On 02.11.2015 21:28, Peter Maydell wrote:
> On 2 November 2015 at 17:51, Sergey Fedorov wrote:
>> CPU singlestep is done by generating a debug internal exception. Do not
>> raise a real CPU exception in case of singlestepping.
>>
>> Signed-off-by: Sergey Fedorov
>&g
On 02.11.2015 21:29, Peter Maydell wrote:
> On 2 November 2015 at 18:16, Sergey Fedorov wrote:
>> AArch32 translation code does not distinguish between DISAS_UPDATE and
>> DISAS_JUMP. Thus, we cannot use any of them without first updating PC in
>> CPU state. Furthermore, it
finishing translation
- DISAS_JUMP: preserve current PC value in CPU state when finishing
translation
Signed-off-by: Sergey Fedorov
---
target-arm/translate.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/target-arm/translate.c b/target
CPU singlestep is done by generating a debug internal exception. Do not
raise a real CPU exception in case of singlestepping.
Signed-off-by: Sergey Fedorov
---
target-arm/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/op_helper.c b/target-arm
On 02.11.2015 14:09, Peter Maydell wrote:
> On 21 October 2015 at 19:15, Sergey Fedorov wrote:
>> On 16.10.2015 16:58, Peter Maydell wrote:
>>> From: Sergey Fedorov
>>>
>>> A QEMU breakpoint match is not definitely an architectural breakpoint
>
On 27.10.2015 14:02, Edgar E. Iglesias wrote:
> On Tue, Oct 27, 2015 at 10:15:32AM +, Peter Maydell wrote:
>> Hi; it's been suggested to me that it would be helpful to have a
>> qemu-arm mailing list, along the lines of the existing qemu-ppc
>> and qemu-block lists. The idea would be to get peo
On 23.10.2015 15:41, Peter Maydell wrote:
> On 23 October 2015 at 13:39, Sergey Fedorov wrote:
>> On 23.10.2015 15:37, Peter Maydell wrote:
>>> On 23 October 2015 at 13:35, Sergey Fedorov wrote:
>>>> On 23.10.2015 14:10, Peter Maydell wrote:
>>>>>
On 23.10.2015 15:37, Peter Maydell wrote:
> On 23 October 2015 at 13:35, Sergey Fedorov wrote:
>> On 23.10.2015 14:10, Peter Maydell wrote:
>>> On 23 October 2015 at 11:14, Sergey Fedorov wrote:
>>>> Thanks, Peter. What if I am going to modify DISAS_JUMP and DISAS_U
On 23.10.2015 14:10, Peter Maydell wrote:
> On 23 October 2015 at 11:14, Sergey Fedorov wrote:
>> Thanks, Peter. What if I am going to modify DISAS_JUMP and DISAS_UPDATE
>> usage in 32-bit ARM code and apply AArch64 semantics to them?
> No objection as long as it all still works
On 23.10.2015 00:28, Peter Maydell wrote:
> On 22 October 2015 at 19:28, Sergey Fedorov wrote:
>> Hi all,
>>
>> I am trying to understand what the difference should be between
>> DISAS_JUMP and DISAS_UPDATE. Actually, these macros have comments in
>> inclu
Hi all,
I am trying to understand what the difference should be between
DISAS_JUMP and DISAS_UPDATE. Actually, these macros have comments in
include/exec/exec-all.h which say that DISAS_JUMP should be used when
only PC was modified dynamically whereas DISAS_UPDATE should be used
when some other CP
On 16.10.2015 16:58, Peter Maydell wrote:
> From: Sergey Fedorov
>
> A QEMU breakpoint match is not definitely an architectural breakpoint
> match. If an exception is generated unconditionally during translation,
> it is hardly possible to ignore it in the debug exception handler.
On 19.10.2015 20:04, Richard Henderson wrote:
> On 10/19/2015 01:04 AM, Sergey Fedorov wrote:
>> On 19.10.2015 01:46, Richard Henderson wrote:
>>> On 10/16/2015 04:08 AM, Sergey Fedorov wrote:
>>>> On 16.10.2015 04:14, Richard Henderson wrote:
>>>>>
On 19.10.2015 01:46, Richard Henderson wrote:
> On 10/16/2015 04:08 AM, Sergey Fedorov wrote:
>> On 16.10.2015 04:14, Richard Henderson wrote:
>>> On 10/16/2015 03:36 AM, Peter Maydell wrote:
>>>> On 14 October 2015 at 22:02, Richard Henderson
>>>>
On 16.10.2015 19:36, Sergey Fedorov wrote:
> On 16.10.2015 17:08, Sergey Fedorov wrote:
>> On 16.10.2015 04:14, Richard Henderson wrote:
>>> On 10/16/2015 03:36 AM, Peter Maydell wrote:
>>>> On 14 October 2015 at 22:02, Richard Henderson wrote:
>>>>>
On 16.10.2015 17:08, Sergey Fedorov wrote:
> On 16.10.2015 04:14, Richard Henderson wrote:
>> On 10/16/2015 03:36 AM, Peter Maydell wrote:
>>> On 14 October 2015 at 22:02, Richard Henderson wrote:
>>>> On 10/15/2015 06:34 AM, Peter Maydell wrote:
>>>>&
On 16.10.2015 04:14, Richard Henderson wrote:
> On 10/16/2015 03:36 AM, Peter Maydell wrote:
>> On 14 October 2015 at 22:02, Richard Henderson wrote:
>>> On 10/15/2015 06:34 AM, Peter Maydell wrote:
This is still the same cryptic comment we have in the
targets which do do this. Can
On 16.10.2015 16:01, Peter Maydell wrote:
> On 13 October 2015 at 10:56, Sergey Fedorov wrote:
>> This series is intended to fix ARM breakpoint emulation misbehavior.
>> QEMU hangs when QEMU breakpoint fires but it does not pass additional
>> architectural checks in AR
On 16.10.2015 15:34, Peter Maydell wrote:
> On 9 October 2015 at 10:43, Sergey Fedorov wrote:
>> Signed-off-by: Sergey Fedorov
>> ---
>>
>> Changes in v2:
>> * Reset value is simply made zero
>>
>> target-arm/cpu.h| 1 +
>> target-ar
On 14.10.2015 22:34, Peter Maydell wrote:
> On 14 October 2015 at 10:35, Sergey Fedorov wrote:
>> On 13.10.2015 20:27, Peter Maydell wrote:
>>> On 9 October 2015 at 10:43, Sergey Fedorov wrote:
>>>> Signed-off-by: Sergey Fedorov
>>>> ---
>>>
The first argument of g_free_rcu() is a pointer to a structure. But
foo_reclaim is used as a function name in the previous example along
with &foo as a pointer to the structure being reclaimed. Make the
example consistent with the previous one.
Signed-off-by: Sergey Fedorov
---
docs/rcu
On 13.10.2015 20:27, Peter Maydell wrote:
> On 9 October 2015 at 10:43, Sergey Fedorov wrote:
>> Signed-off-by: Sergey Fedorov
>> ---
>>
>> Changes in v2:
>> * Reset value is simply made zero
>>
>> target-arm/cpu.h| 1 +
>> target-ar
On 14.10.2015 01:10, Richard Henderson wrote:
> Some targets already had this within their logic, but make sure
> it's present for all targets.
>
> Signed-off-by: Richard Henderson
Reported-by: Sergey Fedorov
Thanks,
Sergey
> ---
> target-alpha/translate.c
On 13.10.2015 03:13, Richard Henderson wrote:
> On 10/10/2015 12:34 AM, Sergey Fedorov wrote:
>>> @@ -2936,6 +2927,10 @@ static inline void
>>> gen_intermediate_code_internal(AlphaCPU *cpu,
>>> tcg_gen_insn_start(ctx.pc);
>>> num
into two parts
* Extra block eliminated in arm_debug_excp_handler()
* Just one instruction always translated in case of breakpoint PC match
Sergey Fedorov (1):
target-arm: Fix CPU breakpoint handling
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 29
GDB breakpoints have higher priority so they have to be checked first.
Should GDB breakpoint match, just return from the debug exception
handler.
Signed-off-by: Sergey Fedorov
---
target-arm/op_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-arm/op_helper.c b/target
breakpoint matches architecturally.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 29 ++---
target-arm/translate-a64.c | 17 -
target-arm/translate.c | 19 ++-
4 files changed, 46
On 08.10.2015 21:40, Peter Maydell wrote:
> Annoying corner case which I don't think we need to handle necessarily:
> if you set a breakpoint on a 32-bit Thumb instruction which spans a page
> boundary, and the second page is not present, we will end up taking the
> page fault when I think we shoul
On 07.10.2015 12:43, Richard Henderson wrote:
> Reduce the boilerplate required for each target. At the same time,
> move the test for breakpoint after calling tcg_gen_insn_start.
>
> Note that arm and aarch64 do not use cpu_breakpoint_test, but still
> move the inline test down after tcg_gen_insn
Signed-off-by: Sergey Fedorov
---
Changes in v2:
* Reset value is simply made zero
target-arm/cpu.h| 1 +
target-arm/helper.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index cc1578c..51d8ed1 100644
--- a/target-arm/cpu.h
+++ b
On 09.10.2015 17:04, Peter Maydell wrote:
> On 9 October 2015 at 14:59, Sergey Fedorov wrote:
>> On 08.10.2015 21:40, Peter Maydell wrote:
>>> Annoying corner case which I don't think we need to handle necessarily:
>>> if you set a breakpoint on a 32-bit Thum
On 09.10.2015 17:04, Peter Maydell wrote:
> On 9 October 2015 at 14:59, Sergey Fedorov wrote:
>> On 08.10.2015 21:40, Peter Maydell wrote:
>>> Annoying corner case which I don't think we need to handle necessarily:
>>> if you set a breakpoint on a 32-bit Thum
On 08.10.2015 21:40, Peter Maydell wrote:
> Annoying corner case which I don't think we need to handle necessarily:
> if you set a breakpoint on a 32-bit Thumb instruction which spans a page
> boundary, and the second page is not present, we will end up taking the
> page fault when I think we shoul
On 09.10.2015 17:00, Peter Maydell wrote:
> On 9 October 2015 at 14:53, Sergey Fedorov wrote:
>> On 08.10.2015 21:40, Peter Maydell wrote:
>>> On 28 September 2015 at 11:07, Sergey Fedorov wrote:
>>>> A QEMU breakpoint match is not definitely an architectura
On 08.10.2015 21:40, Peter Maydell wrote:
> On 28 September 2015 at 11:07, Sergey Fedorov wrote:
>> A QEMU breakpoint match is not definitely an architectural breakpoint
>> match. If an exception is generated unconditionally during translation,
>> it is hardly possible to i
On 29.09.2015 20:24, Sergey Fedorov wrote:
> On 29.09.2015 20:19, Peter Maydell wrote:
>> On 29 September 2015 at 18:14, Sergey Fedorov wrote:
>>> On 29.09.2015 12:33, Peter Maydell wrote:
>>>> On 28 September 2015 at 11:37, Sergey Fedorov wrote:
>>>>
On 29.09.2015 20:19, Peter Maydell wrote:
> On 29 September 2015 at 18:14, Sergey Fedorov wrote:
>> On 29.09.2015 12:33, Peter Maydell wrote:
>>> On 28 September 2015 at 11:37, Sergey Fedorov wrote:
>>> This field should be named mdcr_el2 if we have it, but:
>>&g
On 29.09.2015 12:33, Peter Maydell wrote:
> On 28 September 2015 at 11:37, Sergey Fedorov wrote:
>> Signed-off-by: Sergey Fedorov
>> ---
>>
>> This patch is a prerequisite for a debug exception routing patch:
>> https://lists.gnu.org/archive/html/qemu-devel/20
Signed-off-by: Sergey Fedorov
---
This patch is a prerequisite for a debug exception routing patch:
https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03542.html
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 1 +
target-arm/cpu.h | 1 +
target-arm/cpu64.c | 1 +
target-arm
breakpoint matches architecturally.
Signed-off-by: Sergey Fedorov
---
target-arm/helper.h| 2 ++
target-arm/op_helper.c | 29 ++---
target-arm/translate-a64.c | 14 --
target-arm/translate.c | 13 -
4 files changed, 36 insertions
601 - 700 of 833 matches
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