monitor_puts to rest of code)
Reviwed-by: Xiaoyao Li
Reviewed-by: Markus Armbruster
Signed-off-by: Tao Su
---
v1 -> v2:
- Instead revert the broken part of commit bf0c50d4aa85
- Add Markus's Reviewed-by
v1:
- https://lore.kernel.org/all/20240320052118.520378-1-tao1...@linux.intel.
On Wed, Mar 20, 2024 at 08:17:36AM +0100, Philippe Mathieu-Daudé wrote:
> Hi Tao,
>
> On 20/3/24 07:02, Markus Armbruster wrote:
> > Tao Su writes:
> >
> > > monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
> > > may have a par
On Wed, Mar 20, 2024 at 07:02:46AM +0100, Markus Armbruster wrote:
> Tao Su writes:
>
> > monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
> > may have a parameter with NULL monitor pointer. Check the monitor pointer
> > before calling monit
monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
may have a parameter with NULL monitor pointer. Check the monitor pointer
before calling monitor_puts().
Fixes: bf0c50d4aa85 (monitor: expose monitor_puts to rest of code)
Reviwed-by: Xiaoyao Li
Signed-off-by: Tao Su
doesn’t support TSX and RTM but supports TAA_NO. When RTM is
not enabled in host, KVM will not report TAA_NO. So, just don't include
TAA_NO in SierraForest CPU model.
[1] https://cdrdv2.intel.com/v1/dl/getContent/671368
Reviewed-by: Zhao Liu
Reviewed-by: Xiaoyao Li
Signed-off-by: Tao Su
---
v1
On Wed, Mar 13, 2024 at 02:27:18PM +0100, Gerd Hoffmann wrote:
> Query kvm for supported guest physical address bits, in cpuid
> function 8008, eax[23:16]. Usually this is identical to host
> physical address bits. With NPT or EPT being used this might be
> restricted to 48 (max 4-level
On Fri, Mar 08, 2024 at 05:36:52PM +0100, Igor Mammedov wrote:
> On Wed, 6 Dec 2023 21:19:23 +0800
> Tao Su wrote:
>
> > SierraForest is Intel's first generation E-core based Xeon server
> > processor, which will be released in the first half of 2024.
> >
&
On Tue, Mar 05, 2024 at 11:52:33AM +0100, Gerd Hoffmann wrote:
> Query kvm for supported guest physical address bits, in cpuid
> function 8008, eax[23:16]. Usually this is identical to host
> physical address bits. With NPT or EPT being used this might be
> restricted to 48 (max 4-level
On Mon, Mar 04, 2024 at 09:54:40AM +0800, Xiaoyao Li wrote:
> On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
> > query kvm for supported guest physical address bits using
> > KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
> > (leaf 0x8008, eax, bits 16-23).
> >
> > Signed-off-by:
On Wed, Jan 31, 2024 at 01:34:31PM +0100, Igor Mammedov wrote:
> On Tue, 30 Jan 2024 21:34:36 +0800
> Tao Su wrote:
>
> > On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> > > On Thu, 6 Jul 2023 13:49:49 +0800
> > > Tao Su wrote:
> > &
On Tue, Jan 30, 2024 at 11:14:59AM +0100, Igor Mammedov wrote:
> On Thu, 6 Jul 2023 13:49:49 +0800
> Tao Su wrote:
>
> > The GraniteRapids CPU model mainly adds the following new features
> > based on SapphireRapids:
> > - PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
Kindly ping for any comments.
Thanks,
Tao
are not enabled in KVM mainline yet, will add
them after merged.
Signed-off-by: Tao Su
---
The new features can be found in Intel ISE[1].
LAM has just been accepted by KVM[2].
Although we would like to include all SierraForest features in the first
version of the CPU model, SierraForest
On Wed, Aug 30, 2023 at 12:41:11PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
Thanks Paolo!
the CPUID
definition for AMX-COMPLEX, AMX-COMPLEX will be enabled automatically when
using '-cpu host' and KVM advertises AMX-COMPLEX to userspace.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
KVM part of advertising AMX-COMPLEX CPUID bit already has been applied to
kvm-x86 misc.
[1/1] KVM
On Fri, Jul 07, 2023 at 12:52:37PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
Paolo, thanks!
>
> Paolo
>
://lore.kernel.org/all/63d85cc76d4cdc51e6c732478b81d8f13be11e5a.1687551881.git.pawan.kumar.gu...@linux.intel.com/
Lei Wang (1):
target/i386: Add few security fix bits in ARCH_CAPABILITIES into
SapphireRapids CPU model
Tao Su (5):
target/i386: Add FEAT_7_1_EDX to adjust feature level
target/i386: Add
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions.
Signed-off-by: Tao Su
Reviewed-by: Igor Mammedov
---
target/i386/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386
]
- SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
- FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
Signed-off-by: Tao Su
Tested-by: Xuelian Guo
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 136
feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 26 ++
target/i386/cpu.h | 4
2 files changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
("target/i386: Add support for AVX-VNNI-INT8 in CPUID
enumeration")
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b5688cabb4..952744af97 100644
--- a/target/i386/cpu.c
++
From: Lei Wang
SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
enabled, which are related to some security fixes.
Add version 2 of SapphireRapids CPU model with those bits enabled also.
Signed-off-by: Lei Wang
Signed-off-by: Tao Su
---
target/i386/cpu.c | 13
On Tue, Jun 27, 2023 at 01:55:23PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:11 +0800
> Tao Su wrote:
>
> > The GraniteRapids CPU model mainly adds the following new features based
> > on SapphireRapids:
> >
> > - PREFETCHITI CPUID.(EAX=7,ECX=1)
On Mon, Jun 26, 2023 at 03:03:12PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:07 +0800
> Tao Su wrote:
>
> > MCDT_NO bit indicates HW contains the security fix and doesn't need to
> > be mitigated to avoid data-dependent behaviour for certain instructions.
>
On Mon, Jun 26, 2023 at 02:39:15PM +0200, Igor Mammedov wrote:
> On Fri, 16 Jun 2023 11:23:05 +0800
> Tao Su wrote:
>
> > Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
> > non-zero,
> Can you clarify when/why that happens?
When start a VM on Granit
On Fri, Jun 16, 2023 at 12:01:52PM +0800, Wang, Lei wrote:
> On 6/16/2023 11:23, Tao Su wrote:
> > This patch series mainly updates SapphireRapids CPU model and adds
> > new CPU model EmeraldRapids and GraniteRapids.
> >
> > Bit 13 (ARCH_CAP_FBSDP_NO), bit 14 (AR
in ARCH_CAPABILITIES into
SapphireRapids CPU model
Qian Wen (1):
target/i386: Add new CPU model EmeraldRapids
Tao Su (5):
target/i386: Add FEAT_7_1_EDX to adjust feature level
target/i386: Add support for MCDT_NO in CPUID enumeration
target/i386: Allow MCDT_NO if host supports
target/i386: Add
MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386
Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions
and feature names.
Signed-off-by: Tao Su
---
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git
MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]
Signed-off-by: Tao Su
Tested-by: Xuelian Guo
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 136 ++
1 file changed, 136 insertions
From: Lei Wang
Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
fixes.
Add version 2 of SapphireRapids CPU model with those bits enabled also.
Signed-off-by: Lei Wang
Signed-off-by: Tao Su
---
target/i386
.
Signed-off-by: Qian Wen
Reviewed-by: Xiaoyao Li
Signed-off-by: Tao Su
---
Changes to original patch
(https://lore.kernel.org/qemu-devel/20230515025308.1050277-1-qian@intel.com/)
- Add MSR_ARCH_CAP_SBDR_SSDP_NO, MSR_ARCH_CAP_FBSDP_NO and
MSR_ARCH_CAP_PSDP_NO
---
target/i386/cpu.c | 127
Considering the case of FEAT_7_1_EAX being 0 and FEAT_7_1_EDX being
non-zero, guest may report wrong maximum number sub-leaves in leaf
07H. So add FEAT_7_1_EDX to adjust feature level.
Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID
enumeration")
Signed-off-
feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 26 ++
target/i386/cpu.h | 4
2 files changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
On Wed, Apr 26, 2023 at 02:24:18PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
>
> Paolo
>
Paolo, thanks!
Tao
Intel platforms Granite Rapids/Sierra Forest introduce below new
instructions and CPUID leaves:
- CMPccXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]
- AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
- AVX-VNNI-INT8 CPUID.(EAX=7,ECX=1):EDX[bit 4]
- AVX-NE-CONVERT
without
loss of accuracy or added SW overhead.
The bit definition:
CPUID.(EAX=7,ECX=1):EAX[bit 21]
Add CPUID definition for AMX-FP16.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git
compatibility.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 5]
Add CPUID definition for AVX-NE-CONVERT.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386
):EAX[bit 7]
Add CPUID definition for CMPCCXADD.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4bad3d41d3..e54e13d050 100644
-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index eee1e5c25f..719e6a2636 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -894,7 +894,7
into the
destination dword element size operand.
The bit definition:
CPUID.(EAX=7,ECX=1):EDX[bit 4]
AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word
FEAT_7_1_EDX for this leaf.
Add CPUID definition for AVX-VNNI-INT8.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target
-IFMA.
Signed-off-by: Jiaxi Chen
Signed-off-by: Tao Su
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ed08a52619..9aaa373e97 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
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