iolation
Originated-from: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
include/exec/memory.h | 1 +
target/i386/kvm/tdx.c | 20
2 files changed, 21 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 7229fcc0415f..f25959f6d30f 100644
--- a/incl
s and error out if user wants PIC.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 7eb3628763ae..838b7916278c 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i38
offset of TDX metadata to the end
of firmware file.
Select X86_FW_OVMF when TDX is enable to leverage existing functions
to parse and search OVMF's GUID-ed structures.
Signed-off-by: Isaku Yamahata
Co-developed-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Chang
ITIES, QEMU chooses to try starting with a known number
and abort when it exceeds KVM_MAX_CPUID_ENTRIES.
Besides, introduce the interfaces to invoke TDX "ioctls" at different
scope (KVM, VM and VCPU) in preparation.
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- use {} to initialize str
TDX doesn't support map different GPAs to same private memory. Thus,
aliasing top 128KB of BIOS as isa-bios is not supported.
On the other hand, TDX guest cannot go to real mode, it can work fine
without isa-bios.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v1:
- u
TDX doesn't support SMM and VMM cannot emulate SMM for TDX VMs because
VMM cannot manipulate TDX VM's memory.
Disable SMM for TDX VMs and error out if user requests to enable SMM.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 8
1 file
=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v
Signed-off-by: Isaku Yamahata
Co-developed-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- describe more of there fields in qom.json
- free the old value before set new value to avoid memory leak in
_setter(); (Daniel)
Changes in
From: Isaku Yamahata
TDVF firmware (CODE and VARS) needs to be added/copied to TD's private
memory via KVM_TDX_INIT_MEM_REGION, as well as TD HOB and TEMP memory.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v1:
- rename variable @met
Add docs/system/i386/tdx.rst for TDX support, and add tdx in
confidential-guest-support.rst
Signed-off-by: Xiaoyao Li
---
Changes since v1:
- Add prerequisite of private gmem;
- update example command to launch TD;
Changes since RFC v4:
- add the restriction that kernel-irqchip must be
(). Note, shared
memory can be discarded only when it's not back'ed by hugetlb because
hugetlb is supposed to be pre-allocated and no need for discarding.
Signed-off-by: Chao Peng
Co-developed-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- open-coded ram_block_discard logic
memory.
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- move the check of kvm_supported_memory_attributes to the common
kvm_set_memory_attributes(); (Wang Wei)
- change warn_report() to error_report() in kvm_set_memory_attributes()
and drop the __func__; (Daniel)
---
accel/kvm/kvm-all.c | 44
.pdf
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
include/standard-headers/uefi/uefi.h | 198 +++
1 file changed, 198 insertions(+)
create mode 100644 include/standard-headers/uefi/uefi.h
diff --git a/include/standard-headers/uefi/uefi.h
b/include/standard
From: Isaku Yamahata
When level trigger isn't supported on x86 platform,
forcibly report edge trigger in acpi tables.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
hw/i386/acpi-build.c | 99 ---
hw/i386
LMCE is not supported TDX since KVM doesn't provide emulation for
MSR_IA32_FEAT_CTL.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm-cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
index 9c791b7b0520..8c618869533c 1
Introduce tdx_kvm_init() and invoke it in kvm_confidential_guest_init()
if it's a TDX VM.
Set ms->require_guest_memfd to require kvm guest memfd allocation for any
memory backend. More TDX specific initialization will be added later.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd
.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
hw/i386/x86.c | 1 +
include/hw/i386/x86.h | 1 +
target/i386/kvm/tdx.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index f13f49069d40..504575abfa98 100644
--- a/hw/i386/x86.c
+++ b/hw/i386
TDX only supports readonly for shared memory but not for private memory.
In the view of QEMU, it has no idea whether a memslot is used as shared
memory of private. Thus just mark kvm_readonly_mem_enabled to false to
TDX VM for simplicity.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility
Originated-from: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- refine the documentation; (Markus)
Changes in v3:
- Add docmentation of new type and struct; (Daniel)
- refine the error message handling; (D
From: Chao Peng
Switch to KVM_SET_USER_MEMORY_REGION2 when supported by KVM.
With KVM_SET_USER_MEMORY_REGION2, QEMU can set up memory region that
backend'ed both by hva-based shared memory and guest memfd based private
memory.
Signed-off-by: Chao Peng
Co-developed-by: Xiaoyao Li
Signe
For TDX, the address below 1MB are entirely general RAM. No need to
initialize pc.rom memory region for TDs.
Signed-off-by: Xiaoyao Li
---
This is more as a workaround of the issue that for q35 machine type, the
real memslot update (which requires memslot deletion )for pc.rom happens
after
KVM doesn't allow wirting to MSR_IA32_APICBASE for TDs.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/kvm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 128cce929ed3..109f778ba14d 100644
--- a/target
TD guest can use TDG.VP.VMCALL to request termination
with error message encoded in GPRs.
Parse and print the error message, and terminate the TD guest in the
handler.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 39 +++
target/i386/kvm/tdx.h | 1
TDX CPU state is protected and thus vcpu state cann't be reset by VMM.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index e36ece874246..0ec0584
For TDs, only MSR_IA32_UCODE_REV in kvm_init_msrs() can be configured
by VMM, while the features enumerated/controlled by other MSRs except
MSR_IA32_UCODE_REV in kvm_init_msrs() are not under control of VMM.
Only configure MSR_IA32_UCODE_REV for TDs.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd
From: Sean Christopherson
Move the architectural (for lack of a better term) CPUID leaf generation
to a separate helper so that the generation code can be reused by TDX,
which needs to generate a canonical VM-scoped configuration.
Signed-off-by: Sean Christopherson
Signed-off-by: Xiaoyao Li
From: Isaku Yamahata
MapGPA is a hypercall to convert GPA from/to private GPA to/from shared GPA.
As the conversion function is already implemented as kvm_convert_memory,
wire it to TDX hypercall exit.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c | 2
;ed before TD runs and no need to be accepted runtime.
The TdxRamEntries[] are later used to setup the memory TD resource HOB
that passes memory info from QEMU to TDVF.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v3:
- use enum TdxRamType in struct TdxRamEntry; (Isaku)
ural CPUID leaf generation to separate helper
i386/tdx: Don't get/put guest state for TDX VMs
Xiaoyao Li (47):
linux-headers: Update to Linux v6.8-rc1
RAMBlock: Add support of KVM private guest memfd
HostMem: Add mechanism to opt in kvm guest memfd via MachineState
trace/
From: Isaku Yamahata
In mch_realize(), process PAM initialization before SMRAM initialization so
that later patch can skill all the SMRAM related with a single check.
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
hw/pci-host/q35.c | 19 ++-
1 file changed, 10
Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make
the TD vCPUs runnable once machine initialization is complete.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/kvm/td
TDX cannot support pflash device since it doesn't support read-only
memslot and doesn't support emulation. Load TDVF(OVMF) with -bios option
for TDs.
When boot a TD, besides loading TDVF to the address below 4G, it needs
parse TDVF metadata.
Signed-off-by: Xiaoyao Li
Acked-by: Ger
From: Chao Peng
Allocate private guest memfd memory for BIOS if it's TD VM.
Signed-off-by: Chao Peng
Co-developed-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
---
hw/i386/x86.c | 10 +-
target/i386/kvm/tdx.c | 18 ++
target/i386/kvm/tdx.h | 2 ++
3 files ch
d-off-by: Isaku Yamahata
Co-developed-by: Sean Christopherson
Signed-off-by: Sean Christopherson
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v1:
- drop the code of adding mmio resources since OVMF prepares all the
MMIO hob itself.
---
hw/i386/meson.build | 2 +
and rectifies the previous step);
- add configurable bits (it covers the other part of type #1);
- fix the ones in vmm_fixup;
(Calculated type is ignored since it's determined at runtime).
Co-developed-by: Chenyi Qiang
Signed-off-by: Chenyi Qiang
Signed-off-by: Xiaoyao Li
---
target/i3
For QEMU VMs, PKS is configured via CPUID_7_0_ECX_PKS and PMU is
configured by x86cpu->enable_pmu. Reuse the existing configuration
interface for TDX VMs.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
target/i386/kvm/tdx.c | 13 +
1 file changed, 13 insertions(+)
d
Some bits in TD attributes have corresponding CPUID feature bits. Reflect
the fixed0/1 restriction on TD attributes to their corresponding CPUID
bits in tdx_cpuid_lookup[] as well.
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- reverse the meaning of tdx_caps->attr_fixed0, because value 0
do the stuff.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
hw/i386/tdvf.c | 1 +
include/hw/i386/tdvf.h | 7 +++
target/i386/kvm/tdx.c | 31 +++
3 files changed, 39 insertions(+)
diff --git a/hw/i386/tdvf.c b/hw/i386/tdvf.c
index ff51f40088f0
From: Isaku Yamahata
For TDX KVM use case, Linux guest is the most major one. It requires
sept_ve_disable set. Make it default for the main use case. For other use
case, it can be enabled/disabled via qemu command line.
Signed-off-by: Isaku Yamahata
---
target/i386/kvm/tdx.c | 2 +-
1 file
Guest memfd support in QEMU requires corresponding KVM guest memfd APIs,
which lands in Linux from v6.8-rc1.
Signed-off-by: Xiaoyao Li
---
include/standard-headers/drm/drm_fourcc.h | 10 +-
include/standard-headers/linux/ethtool.h | 41 +++--
.../standard-headers/linux
configure
this bit.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Acked-by: Markus Armbruster
---
Changes in v4:
- collect Acked-by from Markus
Changes in v3:
- update the comment of property @sept-ve-disable to make it more
descriptive and use new format. (Daniel and Markus)
---
qapi
Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM
scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM.
Besides, sanity check the tsc frequency to be in the legal range and
legal granularity (required by TDX module).
Signed-off-by: Xiaoyao
It avoid looking up the machine in phymem.c.
MachineState::require_guest_memfd is supposed to be set by any VMs
that requires KVM guest memfd as private memory, e.g., TDX VM.
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- rename "require_guest_memfd" to "guest_memfd"
QEMU may change the CPUID
configuration when creating vCPUs, i.e. punts on refactoring QEMU to
provide a stable CPUID config prior to kvm_arch_init().
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Acked-by: Markus Armbruster
---
Changes in v4:
- mark init_vm with g_autofree() an
dx0,...
it parses VM type as KVM_X86_TDX_VM. Otherwise, it's KVM_X86_DEFAULT_VM.
Also store the vm_type in MachineState for other code to query what the
VM type is.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v4:
- fix the build error of kvm_get_vm_type() when --dis
Introduce a separate function kvm_confidential_guest_init(), which
dispatches specific confidential guest initialization function by
ms->cgs type.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Reviewed-by: Philippe Mathieu-Daudé
---
target/i386/kvm/kvm.c | 11 ++-
target/i
When memory page is converted from private to shared, the original
private memory is back'ed by guest_memfd. Introduce
ram_block_discard_guest_memfd_range() for discarding memory in
guest_memfd.
Originally-from: Isaku Yamahata
Codeveloped-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
---
Chang
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
---
Changes in v3:
- pass @errp to kvm_arch_pre_create_vcpu(); (Per
It will need special handling for TDX VMs all around the QEMU.
Introduce is_tdx_vm() helper to query if it's a TDX VM.
Cache tdx_guest object thus no need to cast from ms->cgs every time.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Reviewed-by: Isaku Yamahata
---
chang
make Intel-PT unsupported for TD
guest, to avoid the confusing warning.
[1]
https://lore.kernel.org/qemu-devel/20230531084311.3807277-1-xiaoyao...@intel.com/
Signed-off-by: Xiaoyao Li
---
Changes in v4:
- newly added patch;
---
target/i386/kvm/tdx.c | 5 +
1 file changed, 5 insertions(+)
Note, RAM_GUEST_MEMFD is supposed to be set for memory backends of
confidential guests, such as TDX VM. How and when to set it for memory
backends will be implemented in the following patches.
Introduce memory_region_has_guest_memfd() to query if the MemoryRegion has
KVM guest_memfd allocated.
Signed-off-by: Xi
From: Isaku Yamahata
Signed-off-by: Isaku Yamahata
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c| 2 ++
accel/kvm/trace-events | 1 +
2 files changed, 3 insertions(+)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 2421b8a5b314..def2b46b9de2 100644
--- a/accel/kvm/kvm
ed0/1 fields by removing the bits that
reported from TDX module as configurable. This can adapt with the
updated TDX (module) automatically.
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/tdx.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/i386/kvm/
KVM requires userspace to pass XFAM configuration via CPUID 0xD leaves.
Convert tdx_caps->xfam_fixed0/1 into corresponding
tdx_cpuid_lookup[].tdx_fixed0/1 field of CPUID 0xD leaves. Thus the
requirement can be applied naturally.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c |
0 and not
configurable so far.
Signed-off-by: Xiaoyao Li
Acked-by: Gerd Hoffmann
Acked-by: Markus Armbruster
---
Changes in v4:
- update the new qapi `since` filed from 8.2 to 9.0
Changes in v1
- make @attributes not user-settable
---
configs/devices/i386-softmmu/default.mak | 1 +
hw/i3
The upper 16 bits of kvm_userspace_memory_region::slot are
address space id. Parse it separately in trace_kvm_set_user_memory().
Signed-off-by: Xiaoyao Li
---
accel/kvm/kvm-all.c| 5 +++--
accel/kvm/trace-events | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/accel
No such constraint that subleaf index needs to be less than 64.
Signed-off-by: Xiaoyao Li
Reviewed-by:Yang Weijiang
---
target/i386/kvm/kvm.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index dff9dedbd761..9758c83693ec 100644
--- a
master branch
v1:
https://lore.kernel.org/qemu-devel/20220712021249.3227256-1-xiaoyao...@intel.com/
Xiaoyao Li (3):
i386/cpuid: Decrease cpuid_i when skipping CPUID leaf 1F
i386/cpuid: Remove subleaf constraint on CPUID leaf 1F
i386/cpuid: Move leaf 7 to correct group
target/i386/kvm/kvm.c |
Existing code misses a decrement of cpuid_i when skip leaf 0x1F.
There's a blank CPUID entry(with leaf, subleaf as 0, and all fields
stuffed 0s) left in the CPUID array.
It conflicts with correct CPUID leaf 0.
Signed-off-by: Xiaoyao Li
Reviewed-by:Yang Weijiang
---
target/i386/kvm/kvm.
t.
Leaf 7 follows the logic that EAX of subleaf 0 enumerates the maximum
valid subleaf.
Fixes: b9edbadefb9e ("i386: Propagate SGX CPUID sub-leafs to KVM")
Signed-off-by: Xiaoyao Li
---
target/i386/kvm/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/kvm
Use __func__ to avoid hard-coded function name.
Signed-off-by: Xiaoyao Li
Reviewed-by: David Hildenbrand
---
system/physmem.c | 38 +-
1 file changed, 17 insertions(+), 21 deletions(-)
diff --git a/system/physmem.c b/system/physmem.c
index cc68a7976378
On 10/18/2023 9:27 PM, Michael S. Tsirkin wrote:
On Sat, Oct 07, 2023 at 02:58:19AM -0400, Xiaoyao Li wrote:
pc_machine_kvm_type() was introduced by commit e21be724eaf5 ("i386/xen:
add pc_machine_kvm_type to initialize XEN_EMULATE mode") to do Xen
specific initialization by utilizin
On 1/23/2024 11:39 PM, Marcelo Tosatti wrote:
On Sat, Jan 20, 2024 at 05:44:07PM +0800, Xiaoyao Li wrote:
On 1/20/2024 12:14 AM, Marcelo Tosatti wrote:
On Fri, Jan 19, 2024 at 02:46:22PM +0800, Xiaoyao Li wrote:
I'm wondering why CPUID_APM_INVTSC is set as unmigratable_flags. Could
a
On 1/20/2024 12:14 AM, Marcelo Tosatti wrote:
On Fri, Jan 19, 2024 at 02:46:22PM +0800, Xiaoyao Li wrote:
I'm wondering why CPUID_APM_INVTSC is set as unmigratable_flags. Could
anyone explain it?
commit 68bfd0ad4a1dcc4c328d5db85dc746b49c1ec07e
Author: Marcelo Tosatti
Date: Wed May
I'm wondering why CPUID_APM_INVTSC is set as unmigratable_flags. Could
anyone explain it?
When the host supports invtsc, it can be exposed to guest.
When the src VM has invtsc exposed, what will forbid it to be migrated
to a dest that also supports VMs with invtsc exposed?
On 1/15/2024 11:18 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 03:45:58PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 15:45:58 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
On 1/15/2024 1:59 PM, Zhao Liu wrote:
(Also cc
On 1/16/2024 10:19 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 04:13:23AM -0500, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 04:13:23 -0500
From: Xiaoyao Li
Subject: [PATCH 0/2] i386/cpu: Two minor fixes for
x86_cpu_enable_xsave_components()
X-Mailer: git-send-email 2.34.1
The two
The value of FEAT_XSAVE_XCR0_HI leaf and FEAT_XSAVE_XSS_HI leaf also
need to be masked by XCR0 and XSS mask respectively, to make it
logically correct.
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 4 ++
Leaf FEAT_XSAVE_XSS_LO and FEAT_XSAVE_XSS_HI also need to be cleared
when CPUID_EXT_XSAVE is not set.
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/t
The two bugs were introduced when xsaves feature was added by commit
301e90675c3f ("target/i386: Enable support for XSAVES based features").
Xiaoyao Li (2):
i386/cpu: Clear FEAT_XSAVE_XSS_LO/HI leafs when CPUID_EXT_XSAVE is not
available
i386/cpu: Mask with XCR0/XS
On 1/15/2024 1:59 PM, Zhao Liu wrote:
(Also cc "machine core" maintainers.)
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:18:17PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 12:18:17 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
On 1/
On 1/15/2024 2:35 PM, Zhao Liu wrote:
On Mon, Jan 15, 2024 at 02:11:17PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 14:11:17 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
On 1/15/2024 2:12 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15
On 1/15/2024 2:25 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:25:19PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 12:25:19 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode
CPUID[4]
On 1/15/2024 11:40 AM, Zhao Liu wrote
On 1/15/2024 2:12 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:34:12PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 12:34:12 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
Yes, I think it's time to move to default 0x1f.
On 1/15/2024 12:09 PM, Zhao Liu wrote:
Hi Yuan,
On Mon, Jan 15, 2024 at 11:25:24AM +0800, Yuan Yao wrote:
Date: Mon, 15 Jan 2024 11:25:24 +0800
From: Yuan Yao
Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
On Mon, Jan 08, 2024 at 04:27:19PM +0800, Zhao Liu wrote:
From
On 1/15/2024 11:48 AM, Zhao Liu wrote:
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:42:41PM +0800, Xiaoyao Li wrote:
Date: Sun, 14 Jan 2024 22:42:41 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
CPUID[0x801D].EAX[bits 25:14]
On 1/8/2024 4:27
On 1/15/2024 11:40 AM, Zhao Liu wrote:
+{
+uint32_t num_ids = 0;
+
+switch (share_level) {
+case CPU_TOPO_LEVEL_CORE:
+num_ids = 1 << apicid_core_offset(topo_info);
+break;
+case CPU_TOPO_LEVEL_DIE:
+num_ids = 1 << apicid_die_offset(topo_info);
+bre
On 1/15/2024 11:27 AM, Zhao Liu wrote:
On Sun, Jan 14, 2024 at 09:49:18PM +0800, Xiaoyao Li wrote:
Date: Sun, 14 Jan 2024 21:49:18 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhuocheng Ding
On 1/11/2024 4:43 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Wed, Jan 10, 2024 at 05:31:28PM +0800, Xiaoyao Li wrote:
Date: Wed, 10 Jan 2024 17:31:28 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
topo in CPUID[4]
On 1/8/2024 4:27 PM, Zhao Liu
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bi
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
An
On 1/11/2024 4:43 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Wed, Jan 10, 2024 at 05:31:28PM +0800, Xiaoyao Li wrote:
Date: Wed, 10 Jan 2024 17:31:28 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
topo in CPUID[4]
On 1/8/2024 4:27 PM, Zhao Liu
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhuocheng Ding
Introduce cluster-id other than module-id to be consistent with
CpuInstanceProperties.cluster-id, and this avoids the confusion
of parameter names when hotplugging.
I don't think reusing 'cluster' from arm for x86's 'module' is a good
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhuocheng Ding
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so also update APIC ID parsing
rule to support module level. With this support, the conversions with
module level between X86CPUTopoIDs, X86CPUTopoInfo and API
f-by: Binbin Wu
Tested-by: Xuelian Guo
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.h| 7 ++-
target/i386/helper.c | 4
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 18ea755644..598a3fa140 100644
--- a/target/i386/cpu.h
++
On 1/3/2024 5:25 PM, Binbin Wu wrote:
On 12/28/2023 4:51 PM, Xiaoyao Li wrote:
On 7/21/2023 4:08 PM, Binbin Wu wrote:
LAM uses CR3[61] and CR3[62] to configure/enable LAM on user pointers.
LAM uses CR4[28] to configure/enable LAM on supervisor pointers.
For CR3 LAM bits, no additional
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the
c inline uint32_t topo_info_cores_per_pkg(X86CPUTopoInfo *topo_info) {
return topo_info.cores_per_module * topo_info.modules_per_die *
topo_info.dies_per_pkg;
}
so we don't need to care how it calculates.
Besides,
Reviewed-by: Xiaoyao Li
cpus_per_pkg
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1
t index,
uint32_t count,
uint32_t limit;
uint32_t signature[3];
X86CPUTopoInfo topo_info;
+uint32_t cores_per_pkg;
+uint32_t cpus_per_pkg;
I prefer to lps_per_pkg or threads_per_pkg.
Other than it,
Reviewed-by: Xiaoyao Li
topo_info.dies_per_pkg = env->n
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using
On 1/9/2024 10:53 PM, Wang, Wei W wrote:
On Tuesday, January 9, 2024 1:47 PM, Li, Xiaoyao wrote:
On 12/21/2023 9:47 PM, Wang, Wei W wrote:
On Thursday, December 21, 2023 7:54 PM, Li, Xiaoyao wrote:
On 12/21/2023 6:36 PM, Wang, Wei W wrote:
No need to specifically check for KVM_MEMORY_ATTRIBUT
On 12/21/2023 9:47 PM, Wang, Wei W wrote:
On Thursday, December 21, 2023 7:54 PM, Li, Xiaoyao wrote:
On 12/21/2023 6:36 PM, Wang, Wei W wrote:
No need to specifically check for KVM_MEMORY_ATTRIBUTE_PRIVATE there.
I'm suggesting below:
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c inde
On 1/8/2024 10:44 PM, Daniel P. Berrangé wrote:
On Fri, Dec 29, 2023 at 10:30:15AM +0800, Xiaoyao Li wrote:
On 11/16/2023 1:58 AM, Daniel P. Berrangé wrote:
On Wed, Nov 15, 2023 at 02:15:01AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation
On 11/16/2023 1:58 AM, Daniel P. Berrangé wrote:
On Wed, Nov 15, 2023 at 02:15:01AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation Service.
Add property "quote-generation-socket" to tdx-guest, whihc is a property
of type Socket
Binbin Wu
Reviewed-by: Xiaoyao Li
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 97ad229d8b..3a42340730 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -96
On 7/21/2023 4:08 PM, Binbin Wu wrote:
LAM uses CR3[61] and CR3[62] to configure/enable LAM on user pointers.
LAM uses CR4[28] to configure/enable LAM on supervisor pointers.
For CR3 LAM bits, no additional handling needed:
- TCG
LAM is not supported for TCG of target-i386. helper_write_crN(
On 12/22/2023 9:14 PM, Daniel P. Berrangé wrote:
On Fri, Dec 22, 2023 at 11:14:12AM +0800, Xiaoyao Li wrote:
On 12/21/2023 7:05 PM, Daniel P. Berrangé wrote:
On Wed, Nov 15, 2023 at 02:15:01AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation
On 12/21/2023 7:05 PM, Daniel P. Berrangé wrote:
On Wed, Nov 15, 2023 at 02:15:01AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation Service.
Add property "quote-generation-socket" to tdx-guest, whihc is a property
of type Socket
On 12/21/2023 6:36 PM, Wang, Wei W wrote:
On Thursday, December 21, 2023 2:11 PM, Li, Xiaoyao wrote:
On 12/12/2023 9:56 PM, Wang, Wei W wrote:
On Wednesday, November 15, 2023 3:14 PM, Xiaoyao Li wrote:
Introduce the helper functions to set the attributes of a range of
memory to private or
t don't include TAA_NO in SierraForest CPU model.
Currently LAM and LASS are not enabled in KVM mainline yet, will add
them after merged.
Signed-off-by: Tao Su
Reviewed-by: Xiaoyao Li
---
The new features can be found in Intel ISE[1].
LAM has just been accepted by KVM[2].
Although we would li
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