On 3/1/2021 5:48 PM, Andrew Jones wrote:
On Fri, Feb 26, 2021 at 04:41:45PM +0800, Ying Fang wrote:
On 2/25/2021 8:02 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:22PM +0800, Ying Fang wrote:
An accurate cpu topology may help improve the cpu scheduler's decision
making when
On 3/1/2021 11:50 PM, Michael S. Tsirkin wrote:
On Mon, Mar 01, 2021 at 10:39:19AM +0100, Andrew Jones wrote:
On Fri, Feb 26, 2021 at 10:23:03AM +0800, Ying Fang wrote:
On 2/25/2021 7:47 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:26PM +0800, Ying Fang wrote:
Add the processor
On 2/25/2021 8:02 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:22PM +0800, Ying Fang wrote:
An accurate cpu topology may help improve the cpu scheduler's decision
making when dealing with multi-core system. So cpu topology description
is helpful to provide guest with the right view
differences has been
dropped from the commit message of [*]. I'm not sure why.
Will fix that. I will add SOB of you then you can help to comment on it.
Thanks,
drew
On Thu, Feb 25, 2021 at 04:56:27PM +0800, Ying Fang wrote:
Add the Processor Properties Topology Table (PPTT) to present
CPU topology
On 2/25/2021 7:47 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:26PM +0800, Ying Fang wrote:
Add the processor hierarchy node structures to build ACPI information
for CPU topology. Since the private resources may be used to describe
cache hierarchy and it is variable among different
On 2/25/2021 9:25 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 08:54:40PM +0800, Ying Fang wrote:
On 2/25/2021 7:03 PM, Andrew Jones wrote:
Hi Ying Fang,
I don't see any change in this patch from what I have in my
tree, so this should be
From: Andrew Jones
Thanks,
drew
Yes, I
On 2/25/2021 7:16 PM, Andrew Jones wrote:
Hi Ying Fang,
The only difference between this and what I have in my tree[*]
is the removal of the socket node (which has been in the Linux
docs since June 2019). Any reason why you removed that node? In
any case, I think I deserve a bit more credit
On 2/25/2021 7:03 PM, Andrew Jones wrote:
Hi Ying Fang,
I don't see any change in this patch from what I have in my
tree, so this should be
From: Andrew Jones
Thanks,
drew
Yes, I picked it from your qemu branch:
https://github.com/rhdrjones/qemu/commit
Support device tree CPU topology descriptions.
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 38 +-
include/hw/arm/virt.h | 1 +
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 371147f3ae..c133b342b8
is a rework based on Andrew Jones's contribution at
https://lists.gnu.org/archive/html/qemu-arm/2018-07/msg00076.html
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 14 ++
hw/arm/virt.c| 2 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
it also adds any missing parent nodes. We also tweak an error
message of qemu_fdt_add_subnode().
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
include/sysemu/device_tree.h | 1 +
softmmu/device_tree.c| 45
for socket description
(2) build_processor_hierarchy for processor description
(3) build_smt_hierarchy for thread (logic processor) description
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 40 +
include/hw/acpi/acpi-defs.h
Add the Processor Properties Topology Table (PPTT) to present
CPU topology information to the guest. A three-level cpu
topology is built in accord with the linux kernel currently does.
Tested-by: Jiajie Li
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 50
-for-virtual-machines-friend-or-foe-dario-faggioli-suse
[1] https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg02166.html
[2]
https://patchwork.ozlabs.org/project/qemu-devel/cover/20180704124923.32483-1-drjo...@redhat.com
Ying Fang (5):
device_tree: Add qemu_fdt_add_path
hw/arm/virt: Add cpu
Kindly ping for it.
Thanks for Stefan's suggestion, we have re-implement the concept by
introducing the 'retry' feature base on the werror=/rerror= mechanism.
Hope this thread won't be missed. Any comments and reviews are wellcome.
Thanks.
Ying Fang.
On 12/15/2020 8:30 PM, Jiahui Cen wrote
On 11/30/2020 9:00 PM, Peter Maydell wrote:
On Mon, 9 Nov 2020 at 03:05, Ying Fang wrote:
Add the CPUCacheInfo structure to hold cpu cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite
source for "smp_cpus" and "max_cpus",
avoid passing them in function parameters, preferring instead to get
them from the state.
No functional change intended.
Signed-off-by: Andrew Jones
Reviewed-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 9 +
hw/
On 11/9/2020 6:45 PM, Salil Mehta wrote:
Hi Fangying,
A trivial thing. This patch looks bit of a noise in this patch-set. Better
to send it as a separate patch-set and get it accepted.
Hmm, this patch looks like a code reactor for the somewhat confusing
*smp_cpus* which will tidy the code.
On 11/7/2020 1:09 AM, Laszlo Ersek wrote:
On 11/05/20 05:30, Ying Fang wrote:
I see it in Qemu the *loader_start* is fixed at 1 GiB on the
physical address space which points to the DRAM base. In ArmVirtQemu.dsc
PcdDeviceTreeInitialBaseAddress is set 0x4000 with correspondence.
Here I
A helper struct AcpiCacheOffset is introduced to describe the offset
of three level caches. The cache hierarchy is built according to
ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 19 +-
hw/arm/virt-acpi
From: Andrew Jones
The virt machine type has never used the CPU topology parameters, other
than number of online CPUs and max CPUs. When choosing how to allocate
those CPUs the default has been to assume cores. In preparation for
using the other CPU topology parameters let's use an smp_parse
readable and easy to construct.
Cc: Igor Mammedov
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 37 +
include/hw/acpi/aml-build.h | 7 +++
2 files changed, 44 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi
Support devicetree cpu cache information descriptions
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 92 +++
1 file changed, 92 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b6cebb5549..21275e03c2 100644
--- a/hw/arm/virt.c
+++ b
Add the CPUCacheInfo structure to hold cpu cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these values.
Signed-off-by: Ying Fang
---
target/arm/cpu.c | 42
From: Andrew Jones
Prefer to spell out the smp.cpus and smp.max_cpus machine state
variables in order to make grepping easier and to avoid any
confusion as to what cpu count is being used where.
Signed-off-by: Andrew Jones
---
hw/arm/virt-acpi-build.c | 8 +++
hw/arm/virt.c|
is a rework based on Andrew Jones's contribution at
https://lists.gnu.org/archive/html/qemu-arm/2018-07/msg00076.html
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 17 -
hw/arm/virt.c| 3 +++
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt
Add 5.3 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 15 ++-
hw/i386/pc_q35.c | 14
From: Andrew Jones
We no longer use the smp_cpus virtual machine state variable.
Remove it.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 2 --
include/hw/arm/virt.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0069fa1298..ea24b576c6
Add the Processor Properties Topology Table (PPTT) to present cpu topology
information to the guest.
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 42
1 file changed, 42 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi
smp.cpus and smp.max_cpus
hw/arm/virt: Remove unused variable
hw/arm/virt: Replace smp_parse with one that prefers cores
device_tree: Add qemu_fdt_add_path
hw/arm/virt: DT: add cpu-map
Ying Fang (8):
hw: add compat machines for 5.3
hw/arm/virt-acpi-build: distinguish possible and pre
To build cache information, An AcpiCacheInfo structure is defined to
hold the type 1 cache structure according to ACPI spec v6.3 5.2.29.2.
A helper function build_cache_hierarchy is also introduced to encode
the cache information.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 26
From: Andrew Jones
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
it also adds any missing parent nodes. We also tweak an error
message of qemu_fdt_add_subnode().
We'll make use of the new function in a coming patch.
Signed-off-by: Andrew Jones
---
device_tree.c
From: Andrew Jones
Support devicetree CPU topology descriptions.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 40 +++-
include/hw/arm/virt.h | 1 +
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/hw/arm
On 11/5/2020 5:46 AM, Laszlo Ersek wrote:
+Ard, +Drew
On 11/03/20 13:39, Igor Mammedov wrote:
On Fri, 30 Oct 2020 10:50:01 +0800
Ying Fang wrote:
Hi,
I have a question on UEFI/ACPI tables setup and probing on arm64 platform.
CCing Laszlo,
who might know how it's implemented
On 10/30/2020 1:20 AM, Andrew Jones wrote:
You need to remove 'Message' from the summary.
On Tue, Oct 20, 2020 at 09:14:34PM +0800, Ying Fang wrote:
When building ACPI tables regarding CPUs we should always build
them for the number of possible CPUs, not the number of present
CPUs. We
On 10/30/2020 12:56 AM, Andrew Jones wrote:
On Tue, Oct 20, 2020 at 09:14:36PM +0800, Ying Fang wrote:
Add the Processor Properties Topology Table (PPTT) to present CPU topology
information to the guest.
Signed-off-by: Andrew Jones
I don't know why I have an s-o-b here. I guess it's
On 10/30/2020 1:24 AM, Andrew Jones wrote:
On Tue, Oct 20, 2020 at 09:14:35PM +0800, Ying Fang wrote:
Add the processor hierarchy node structures to build ACPI information
for CPU topology. Three helpers are introduced:
(1) build_socket_hierarchy for socket description structure
(2
On 10/30/2020 1:08 AM, Andrew Jones wrote:
On Tue, Oct 20, 2020 at 09:14:32PM +0800, Ying Fang wrote:
Add 5.2 machine types for arm/i440fx/q35/s390x/spapr.
^ 5.3
Thanks. Will fix, careless spelling mistake.
Thanks,
drew
Signed-off-by: Ying Fang
---
hw/arm/virt.c
On 10/30/2020 1:20 AM, Andrew Jones wrote:
You need to remove 'Message' from the summary.
On Tue, Oct 20, 2020 at 09:14:34PM +0800, Ying Fang wrote:
When building ACPI tables regarding CPUs we should always build
them for the number of possible CPUs, not the number of present
CPUs. We
Hi,
I have a question on UEFI/ACPI tables setup and probing on arm64 platform.
Currently on arm64 platform guest can be booted with both fdt and ACPI
supported. If ACPI is enabled, [1] says the only defined method for
passing ACPI tables to the kernel is via the UEFI system configuration
table.
A helper struct AcpiCacheOffset is introduced to describe the offset
of three level caches. The cache hierarchy is built according to
ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 19 +-
hw/arm/virt-acpi
From: Andrew Jones
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
it also adds any missing parent nodes. We also tweak an error
message of qemu_fdt_add_subnode().
We'll make use of the new function in a coming patch.
Signed-off-by: Andrew Jones
---
device_tree.c
From: Andrew Jones
The virt machine type has never used the CPU topology parameters, other
than number of online CPUs and max CPUs. When choosing how to allocate
those CPUs the default has been to assume cores. In preparation for
using the other CPU topology parameters let's use an smp_parse
When building ACPI tables regarding CPUs we should always build
them for the number of possible CPUs, not the number of present
CPUs. We then ensure only the present CPUs are enabled.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 17 -
1
Add 5.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 15 ++-
hw/i386/pc_q35.c | 14
Add the Processor Properties Topology Table (PPTT) to present CPU topology
information to the guest.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 42
1 file changed, 42 insertions(+)
diff --git a/hw/arm/virt-acpi
To build cache information, An AcpiCacheInfo structure is defined to
hold the Type 1 cache structure according to ACPI spec v6.3 5.2.29.2.
A helper function build_cache_hierarchy is introduced to encode the
cache information.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 26
) description structure
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 37 +
include/hw/acpi/aml-build.h | 7 +++
2 files changed, 44 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index
From: Andrew Jones
Support devicetree CPU topology descriptions.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 40 +++-
include/hw/arm/virt.h | 1 +
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/hw/arm
Support devicetree CPU cache information descriptions
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 92 +++
1 file changed, 92 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d23b941020..adcfa52854 100644
--- a/hw/arm/virt.c
+++ b
Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these values.
Signed-off-by: Ying Fang
---
target/arm/cpu.c | 42
From: Andrew Jones
Prefer to spell out the smp.cpus and smp.max_cpus machine state
variables in order to make grepping easier and to avoid any
confusion as to what cpu count is being used where.
Signed-off-by: Andrew Jones
---
hw/arm/virt-acpi-build.c | 8 +++
hw/arm/virt.c|
From: Andrew Jones
We no longer use the smp_cpus virtual machine state variable.
Remove it.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 2 --
include/hw/arm/virt.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0069fa1298..ea24b576c6
ble
hw/arm/virt: Replace smp_parse with one that prefers cores
device_tree: Add qemu_fdt_add_path
hw/arm/virt: DT: add cpu-map
Ying Fang (8):
hw: add compat machines for 5.3
hw/arm/virt-acpi-build: distinguish possible and present cpus Message
hw/acpi/aml-build: add processor hierarchy n
On 10/16/2020 6:07 PM, Andrew Jones wrote:
On Fri, Oct 16, 2020 at 05:40:02PM +0800, Ying Fang wrote:
On 10/15/2020 3:59 PM, Andrew Jones wrote:
On Thu, Oct 15, 2020 at 10:07:16AM +0800, Ying Fang wrote:
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM
On 10/15/2020 3:59 PM, Andrew Jones wrote:
On Thu, Oct 15, 2020 at 10:07:16AM +0800, Ying Fang wrote:
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
Cc valentin
-Original Message-
From: Qemu-devel
[mailto:qemu-devel
On 10/10/2020 10:27 AM, cenjiahui wrote:
Hi Kevin,
Could you please spend some time reviewing and commenting on this patch series.
Thanks,
Jiahui Cen
This feature is confirmed effective in a cloud storage environment since
it can help to improve the availability without pausing the entire
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
Cc valentin
-Original Message-
From: Qemu-devel
[mailto:qemu-devel-bounces+prime.zeng=hisilicon@nongnu.org]
On Behalf Of Ying Fang
Sent: Thursday, September 17, 2020 11:20 AM
Sometimes hypervisor management tools like libvirt may need to monitor
I/O hang events. Let's report I/O hang and I/O hang timeout event via qapi.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 3 +++
qapi/block-core.json | 26 ++
2
situations,
the returned error is often an EIO.
To avoid this unavailablity, we can store the failed AIOs, and resend them
later. If the error is temporary, the retries can succeed and the AIOs can
be successfully completed.
Signed-off-by: Ying Fang
Signed-off-by: Jiahui Cen
---
block/block
All AIOs including the hanging AIOs need to be drained when resetting
virtio-blk. So it is necessary to disable I/O hang before resetting
and enable I/O hang again after resetting if I/O hang is enabled.
Signed-off-by: Ying Fang
Signed-off-by: Jiahui Cen
---
hw/block/virtio-blk.c | 8
-off-by: Ying Fang
---
block/block-backend.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index 24dd0670d1..bf104a7cf5 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -35,6 +35,18 @@
static AioContext
Not all errors would be fixed, so it is better to add a rehandle timeout
for I/O hang.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 99 +-
include/sysemu/block-backend.h | 2 +
2 files changed, 100 insertions(+), 1
I/O hang timeout should be different under different situations. So it is
better to provide an option for user to determine I/O hang timeout for
each block device.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
blockdev.c | 11 +++
1 file changed, 11 insertions(+)
diff --git
smoothly when I/O is recovred with this feature enabled.
Ying Fang (7):
block-backend: introduce I/O rehandle info
block-backend: rehandle block aios when EIO
block-backend: add I/O hang timeout
block-backend: add I/O hang drain when disbale
virtio-blk: disable I/O hang when resetting
To disable I/O hang, all hanging AIOs need to be drained. A rehandle status
field is introduced to notify rehandle mechanism not to rehandle failed AIOs
when I/O hang is disabled.
Signed-off-by: Ying Fang
Signed-off-by: Jiahui Cen
---
block/block-backend.c | 85
On 9/17/2020 4:27 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:28AM +0800, Ying Fang wrote:
Add the processor hierarchy node structures to build ACPI information
for CPU topology. Three helpers are introduced:
(1) build_socket_hierarchy for socket description structure
(2
On 9/17/2020 4:39 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:30AM +0800, Ying Fang wrote:
Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite
On 9/17/2020 4:20 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:27AM +0800, Ying Fang wrote:
When building ACPI tables regarding CPUs we should always build
them for the number of possible CPUs, not the number of present
CPUs. We then ensure only the present CPUs are enabled.
Signed
On 9/17/2020 4:12 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:25AM +0800, Ying Fang wrote:
From: Andrew Jones
qemu_fdt_add_path works like qemu_fdt_add_subnode, except it
also recursively adds any missing parent nodes.
Cc: Peter Crosthwaite
Cc: Alexander Graf
Signed-off
On 9/17/2020 4:07 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:24AM +0800, Ying Fang wrote:
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR from userspace, so that
MPIDR is consistent with CPU topology
On 9/17/2020 6:59 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 09:53:35AM +0200, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:23AM +0800, Ying Fang wrote:
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR
On 9/17/2020 3:53 PM, Andrew Jones wrote:
On Thu, Sep 17, 2020 at 11:20:23AM +0800, Ying Fang wrote:
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR from userspace, so that
MPIDR is consistent with CPU topology
A helper struct AcpiCacheOffset is introduced to describe the offset
of three level caches. The cache hierarchy is built according to
ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now.
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 19
To build cache information, An AcpiCacheInfo structure is defined to
hold the Type 1 cache structure according to ACPI spec v6.3 5.2.29.2.
A helper function build_cache_hierarchy is introduced to encode the
cache information.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 26
Support devicetree CPU cache information descriptions
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 71f7dbb317..74b748ae35 100644
--- a/hw/arm/virt.c
+++ b
Add the Processor Properties Topology Table (PPTT) to present CPU topology
information to the guest.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 42
1 file changed, 42 insertions(+)
diff --git a/hw/arm/virt-acpi
] https://patchwork.kernel.org/cover/11781317
[2]
https://patchwork.ozlabs.org/project/qemu-devel/cover/20180704124923.32483-1-drjo...@redhat.com
Andrew Jones (2):
device_tree: add qemu_fdt_add_path
hw/arm/virt: DT: add cpu-map
Ying Fang (10):
linux headers: Update linux header
) description structure
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 37 +
include/hw/acpi/aml-build.h | 7 +++
2 files changed, 44 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index
When building ACPI tables regarding CPUs we should always build
them for the number of possible CPUs, not the number of present
CPUs. We then ensure only the present CPUs are enabled.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 17 -
1
Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these values.
Signed-off-by: Ying Fang
---
target/arm/cpu.c | 42
Signed-off-by: Ying Fang
---
linux-headers/linux/kvm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index a28c366737..461a2302e7 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1031,6 +1031,7 @@ struct
From: Andrew Jones
qemu_fdt_add_path works like qemu_fdt_add_subnode, except it
also recursively adds any missing parent nodes.
Cc: Peter Crosthwaite
Cc: Alexander Graf
Signed-off-by: Andrew Jones
---
device_tree.c| 24
include/sysemu/device_tree.h |
From: Andrew Jones
Support devicetree CPU topology descriptions.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 37 -
include/hw/arm/virt.h | 1 +
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR from userspace, so that
MPIDR is consistent with CPU topology configured.
Signed-off-by: Ying Fang
---
target/arm/kvm64.c | 46
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR from userspace, so that
MPIDR is consistent with CPU topology configured.
Signed-off-by: Ying Fang
---
target/arm/kvm32.c | 46
On 8/7/2020 4:13 PM, Kevin Wolf wrote:
Am 07.08.2020 um 09:42 hat Ying Fang geschrieben:
On 8/6/2020 5:13 PM, Kevin Wolf wrote:
Am 05.08.2020 um 04:38 hat Ying Fang geschrieben:
From: fangying
When qemu or qemu-nbd process uses a qcow2 image and configured with
'cache = none
On 8/6/2020 5:13 PM, Kevin Wolf wrote:
Am 05.08.2020 um 04:38 hat Ying Fang geschrieben:
From: fangying
When qemu or qemu-nbd process uses a qcow2 image and configured with
'cache = none', it will write to the qcow2 image with a cache to cache
L2 tables, however the process will not use L2
On 8/5/2020 10:43 AM, no-re...@patchew.org wrote:
Patchew URL: https://patchew.org/QEMU/20200805023826.184-1-fangyi...@huawei.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can
On 8/6/2020 2:01 PM, Michael S. Tsirkin wrote:
On Thu, Aug 06, 2020 at 11:56:32AM +0800, Ying Fang wrote:
From: fangying
Hi, this patchset was previously posted by my teamate Heyi Guo several
months ago, however we missed the merge window. It is reposted here to
make it an end. Thanks
ly for the max speed and current speed of processor, for
"max speed" identifies a capability of the system, and "current speed"
identifies the processor's speed at boot (see smbios spec), but some
applications do not tell the differences.
Reviewed-by: Igor Mammedov
Signed-off-by: Yin
ption names to "-"
- check if option value is too large to fit in SMBIOS type 4 speed
fields.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Ying Fang (2):
hw/smbios: add options for type 4 max-speed and current-speed
tests/bios-tables-test: add smbios cpu speed test
hw/
t
doesn't really run on aarch64 platform for smbios test can't run on
uefi only platform yet.
Signed-off-by: Ying Fang
Signed-off-by: Heyi Guo
---
tests/bios-tables-test.c | 42
1 file changed, 42 insertions(+)
diff --git a/tests/bios-tables-test.c b/tests/bios
cluster.
Signed-off-by: Ying Fang
diff --git a/block/qcow2-cache.c b/block/qcow2-cache.c
index 7444b9c..ab6e812 100644
--- a/block/qcow2-cache.c
+++ b/block/qcow2-cache.c
@@ -266,6 +266,22 @@ int qcow2_cache_flush(BlockDriverState *bs, Qcow2Cache *c)
return result;
}
+#define
On 6/10/2020 3:40 PM, Andrew Jones wrote:
On Wed, Jun 10, 2020 at 09:32:06AM +0800, Ying Fang wrote:
On 6/8/2020 8:49 PM, Andrew Jones wrote:
On Mon, Jun 08, 2020 at 08:12:43PM +0800, Ying Fang wrote:
From: fangying
Virtual time adjustment was implemented for virt-5.0 machine type
On 6/8/2020 8:49 PM, Andrew Jones wrote:
On Mon, Jun 08, 2020 at 08:12:43PM +0800, Ying Fang wrote:
From: fangying
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu which
From: fangying
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu which has the generic timer
feature enabled.
Suggested-by: Andrew Jones
Signed-off-by: Ying Fang
---
v3
ping
On 6/4/2020 4:51 PM, Ying Fang wrote:
Hi Richard,
Recently we are doing some tests on forward migration based on
arm virt machine. And we found the patch below breaks forward
migration compatibility from virt-4.2 to virt-5.0 above machine
type. The patch which breaks this down given
On 6/3/2020 4:53 PM, Andrew Jones wrote:
On Tue, Jun 02, 2020 at 03:47:22PM +0800, Ying Fang wrote:
On 2020/6/1 20:29, Andrew Jones wrote:
On Mon, Jun 01, 2020 at 08:07:31PM +0800, Ying Fang wrote:
On 2020/6/1 16:07, Andrew Jones wrote:
On Sat, May 30, 2020 at 04:56:26PM +0800, Ying
Hi Richard,
Recently we are doing some tests on forward migration based on
arm virt machine. And we found the patch below breaks forward
migration compatibility from virt-4.2 to virt-5.0 above machine
type. The patch which breaks this down given by git bisect is
commit
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