On 2023/2/4 1:18, Richard Henderson wrote:
'offset' should be bits [23:5] of LDR instruction, rather than [4:0].
Fixes: d59d83a1c388 ("tcg/aarch64: Reorg goto_tb implementation")
Reported-by: Zenghui Yu
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 2 +-
1 file changed,
On 2023/1/18 7:10, Richard Henderson wrote:
+void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
+ uintptr_t jmp_rx, uintptr_t jmp_rw)
+{
+uintptr_t d_addr = tb->jmp_target_addr[n];
+ptrdiff_t d_offset = d_addr - jmp_rx;
+tcg_insn_unit insn;
+
Hi Alexander,
On 2022/12/23 17:01, Alexander Graf wrote:
Let's explicitly list out all accelerators that we support when trying to
determine the supported set of GIC versions. KVM was already separate, so
the only missing one is HVF which simply reuses all of TCG's emulation
code and thus has th
On 2022/12/23 17:01, Alexander Graf wrote:
Up to now, the finalize_gic_version() code open coded what is essentially
a support bitmap match between host/emulation environment and desired
target GIC type.
This open coding leads to undesirable side effects. For example, a VM with
KVM and -smp 10 w
On 2022/12/21 7:04, Alexander Graf wrote:
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index c7dd59d7f1..365d19f7a3 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -109,12 +109,12 @@ typedef enum VirtMSIControllerType {
} VirtMSIControllerType;
typedef enum Vir
[ +Eric who wrote finalize_gic_version() ]
On 2022/12/21 7:04, Alexander Graf wrote:
The finalize_gic_version() function tries to determine which GIC version
the current accelerator / host combination supports. During the initial
HVF porting efforts, I didn't realize that I also had to touch thi
On 2022/12/20 15:37, Alexander Graf wrote:
Hi Zenghui,
On 20.12.22 08:14, Zenghui Yu wrote:
On 2022/12/20 6:08, Alexander Graf wrote:
We currently only support GICv2 emulation.
Before looking into it, I think it's worth finalizing the GIC version in
the hvf case - only v2 is allowed and fail
On 2022/12/20 6:08, Alexander Graf wrote:
We currently only support GICv2 emulation.
Before looking into it, I think it's worth finalizing the GIC version in
the hvf case - only v2 is allowed and fail early if user selects the
unsupported versions. Currently finalize_gic_version() does not deal
[ Fix Marc's email address ]
On 2022/9/13 21:56, Richard Henderson wrote:
We had only been reporting the stage2 page size. This causes
problems if stage1 is using a larger page size (16k, 2M, etc),
but stage2 is using a smaller page size, because cputlb does
not set large_page_{addr,mask} prope
Hi Eric,
On 2022/9/20 17:23, Eric Auger wrote:
Hi Zenghui,
On 9/19/22 16:30, Zenghui Yu wrote:
Hi Eric,
A few comments when looking through the PMU test code (2 years after
the series was merged).
Thank you for reviewing even after this time! Do you want to address the
issues yourself and s
Hi Eric,
On 2020/4/3 15:13, Eric Auger wrote:
+static void test_chain_promotion(void)
+{
[...]
+ /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */
+ pmu_reset();
+ write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0);
+ write_regn_el0(pmev
Hi Eric,
On 2020/4/3 15:13, Eric Auger wrote:
+static void test_sw_incr(void)
+{
+ uint32_t events[] = {SW_INCR, SW_INCR};
+ int i;
+
+ if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
+ return;
+
+ pmu_reset();
+
+ write_regn_el0(pmevtyper, 0,
Hi Eric,
A few comments when looking through the PMU test code (2 years after
the series was merged).
On 2020/4/3 15:13, Eric Auger wrote:
Adds the following tests:
- event-counter-config: test event counter configuration
- basic-event-count:
- programs counters #0 and #1 to count 2 required
On 2022/8/11 21:11, Peter Maydell wrote:
The newly added neoverse-n1 CPU has ID register values which indicate
the presence of the Statistical Profiling Extension, because the real
hardware has this feature. QEMU's TCG emulation does not yet
implement SPE, though (not even as a minimal stub impl
With the introduction of the new TCG GICv4, build_madt() is badly broken
as we do not present any GIC Redistributor structure in MADT for GICv4
guests, so that they have no idea about where the Redistributor
register frames are. This fixes a Linux guest crash at boot time with
ACPI enabled and '-ma
On 2022/8/11 0:47, Peter Maydell wrote:
On Wed, 10 Aug 2022 at 14:14, Zenghui Yu wrote:
The r4p1 TRM says that the Neoverse N1 core supports SPE (the value
of ID_AA64DFR0.PMSVer is 0b0001) but do we really support SPE
emulation in QEMU?
The guest immediately received an unexpected exception (w
On 2022/5/7 2:02, Richard Henderson wrote:
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+ARMCPU *cpu = ARM_CPU(obj);
+
+cpu->dtb_compatible = "arm,neoverse-n1";
+set_feature(&cpu->env, ARM_FEATURE_V8);
+set_feature(&cpu->env, ARM_FEATURE_NEON);
+set_feature(&cpu->e
Hi Richard,
On 2022/7/26 2:14, Richard Henderson wrote:
Indication for support for SVE will not depend on whether we
perform the query on the main kvm_state or the temp vcpu.
Mirror kvm_arm_pauth_supported.
Signed-off-by: Richard Henderson
---
target/arm/kvm64.c | 7 ++-
1 file changed, 6
Hi Richard,
On 2021/5/25 9:02, Richard Henderson wrote:
Will be used for SVE2 isa subset enablement.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
v2: Do not read zfr0 from kvm unless sve is available.
v7: Move zfr0 read inside existing sve_enabled block.
[...]
diff --git
On 2022/5/26 0:19, Philippe Mathieu-Daudé wrote:
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 86710509d2..1fdc5eef92 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -17,6 +17,7 @@
#include "sysemu/hvf_int.h"
#include "sysemu/hw_accel.h"
#include "hvf_arm.h"
+#
On 2022/1/27 14:34, Richard Henderson wrote:
Use the named bit rather than a bare extract32.
Signed-off-by: Richard Henderson
Reviewed-by: Zenghui Yu
On 2022/1/27 14:34, Richard Henderson wrote:
Extract entire fields for ZEN and FPEN, rather than testing specific bits.
This makes it easier to follow the code versus the ARM spec.
Signed-off-by: Richard Henderson
Reviewed-by: Zenghui Yu
Hi Richard,
On 2022/1/27 14:34, Richard Henderson wrote:
+if (el <= 2) {
+if (hcr_el2 & HCR_E2H) {
+/* Check CPTR_EL2.ZEN. */
+switch (extract32(env->cp15.cptr_el[2], 16, 2)) {
+case 1:
+if (el != 0 || !(hcr_el2 & HCR_TGE)) {
It
On 2022/1/27 14:34, Richard Henderson wrote:
When HCR_EL2.{E2H,TGE} == '11', ZCR_EL1 is unused.
Reported-by: Zenghui Yu
Signed-off-by: Richard Henderson
Reviewed-by: Zenghui Yu
Hi,
I've just exercised the SVE emulation in QEMU with
| `qemu-system-aarch64 -M virt,virtualization=on,gic-version=3 \
| -cpu max -accel tcg [...]`
Since QEMU sets ID_AA64MMFR1_EL1.VH for -cpu max, the Linux guest I use
was booting with VHE enabled and running with E2H+TGE. But I've then
seen
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