Re: [Qemu-devel] Making TCG configurable in system mode

On Wed, Dec 14, 2016 at 10:51 PM, Paolo Bonzini wrote: > >> I am looking at the possibility to add a new QEMU configuration option >> to make TCG optional (in qemu-system-*). What I am exploring is a way >> to exclude any of the TCG code not needed by KVM from the QEMU

[Qemu-devel] Making TCG configurable in system mode

Hi all, I am looking at the possibility to add a new QEMU configuration option to make TCG optional (in qemu-system-*). What I am exploring is a way to exclude any of the TCG code not needed by KVM from the QEMU binary. There has been a previous attempt in the past from Paolo Bonzini, namely

Re: [Qemu-devel] [RFC 7/8] cpu-exec-common: Introduce async_safe_run_on_cpu()

Hi Sergey, On Mon, Jun 20, 2016 at 12:28 AM, Sergey Fedorov <sergey.fedo...@linaro.org> wrote: > > From: Sergey Fedorov <serge.f...@gmail.com> > > This patch is based on the ideas found in work of KONRAD Frederic [1], > Alex Bennée [2], and Alvise Rigo [3]. > >

Re: [Qemu-devel] Any topics for today's MTTCG sync-up call?

On Mon, Jun 20, 2016 at 4:12 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > alvise rigo <a.r...@virtualopensystems.com> writes: > > > Hi Alex, > > > > I'm looking into the worries that Sergey issued in his review of the > > last LL/SC series. The

Re: [Qemu-devel] Any topics for today's MTTCG sync-up call?

Hi Alex, I'm looking into the worries that Sergey issued in his review of the last LL/SC series. The target is to reduce the TLB flushes by using an exclusive history of dynamic length. I don't have anything ready yet though. Best regards, alvise On Mon, Jun 20, 2016 at 1:57 PM, Alex Bennée

Re: [Qemu-devel] exec: Safe work in quiescent state

On Wed, Jun 15, 2016 at 4:51 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > alvise rigo <a.r...@virtualopensystems.com> writes: > >> Hi Sergey, >> >> Nice review of the implementations we have so far. >> Just few comments below. >> >>

Re: [Qemu-devel] exec: Safe work in quiescent state

Hi Sergey, Nice review of the implementations we have so far. Just few comments below. On Wed, Jun 15, 2016 at 2:59 PM, Sergey Fedorov wrote: > On 10/06/16 00:51, Sergey Fedorov wrote: >> For certain kinds of tasks we might need a quiescent state to perform an >> operation

Re: [Qemu-devel] [RFC 02/10] softmmu_llsc_template.h: Move to multi-threading

, 2016 at 2:00 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > alvise rigo <a.r...@virtualopensystems.com> writes: > >> On Fri, Jun 10, 2016 at 5:21 PM, Sergey Fedorov <serge.f...@gmail.com> wrote: >>> On 26/05/16 19:35, Alvise Rigo wrote: >>>> U

Re: [Qemu-devel] [RFC 02/10] softmmu_llsc_template.h: Move to multi-threading

This would require to fill again the whole history which I find very unlikely. In any case, this has to be documented. Thank you, alvise On Fri, Jun 10, 2016 at 6:00 PM, Sergey Fedorov <serge.f...@gmail.com> wrote: > On 10/06/16 18:53, alvise rigo wrote: >> On Fri, Jun 10,

Re: [Qemu-devel] [RFC 02/10] softmmu_llsc_template.h: Move to multi-threading

On Fri, Jun 10, 2016 at 5:21 PM, Sergey Fedorov <serge.f...@gmail.com> wrote: > On 26/05/16 19:35, Alvise Rigo wrote: >> Using tcg_exclusive_{lock,unlock}(), make the emulation of >> LoadLink/StoreConditional thread safe. >> >> During an LL access, this loc

Re: [Qemu-devel] [RFC 00/10] MTTCG: Slow-path for atomic insns

I might have broken something while rebasing on top of enable-mttcg-for-armv7-v1. I will sort this problem out. Thank you, alvise On Fri, Jun 10, 2016 at 5:21 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >>

Re: [Qemu-devel] [RFC v8 00/14] Slow-path for atomic instruction translation

Hi Sergey, Thank you for this precise summary. On Thu, Jun 9, 2016 at 1:42 PM, Sergey Fedorov <serge.f...@gmail.com> wrote: > Hi, > > On 19/04/16 16:39, Alvise Rigo wrote: >> This patch series provides an infrastructure for atomic instruction >> implementation in QE

Re: [Qemu-devel] [RFC 03/10] cpus: Introduce async_wait_run_on_cpu()

e. alvise On Wed, Jun 8, 2016 at 5:20 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Sergey Fedorov <serge.f...@gmail.com> writes: > >> On 08/06/16 17:10, alvise rigo wrote: >>> Using run_on_cpu() we might deadlock QEMU if other vCPUs are waiting >>> f

Re: [Qemu-devel] [RFC 03/10] cpus: Introduce async_wait_run_on_cpu()

Using run_on_cpu() we might deadlock QEMU if other vCPUs are waiting for the current vCPU. We need to exit from the vCPU loop in order to avoid this. Regards, alvise On Wed, Jun 8, 2016 at 3:54 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensyst

Re: [Qemu-devel] [RFC 01/10] exec: Introduce tcg_exclusive_{lock, unlock}()

e pretty much confined to the locking/unlocking of a spinlock/mutex. This made me think, how does linux-user can properly work with upstream TCG, for instance, in an absurd configuration like target-arm on ARM host? alvise On Wed, Jun 8, 2016 at 11:21 AM, Alex Bennée <alex.ben...@linaro.org>

Re: [Qemu-devel] [RFC 01/10] exec: Introduce tcg_exclusive_{lock, unlock}()

Hi Pranith, Thank you for the hint, I will keep this in mind for the next version. Regards, alvise On Tue, May 31, 2016 at 5:03 PM, Pranith Kumar <bobby.pr...@gmail.com> wrote: > Hi Alvise, > > On Thu, May 26, 2016 at 12:35 PM, Alvise Rigo > <a.r...@virtualopensyste

[Qemu-devel] [RFC 06/10] cputlb: Add tlb_tables_flush_bitmap()

Add a simple helper function to flush the TLB at the indexes specified by a bitmap. The function will be more useful in the following patches, when it will be possible to query tlb_flush_by_mmuidx() to VCPUs. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.

[Qemu-devel] [RFC 10/10] cpus: Do not sleep if some work item is pending

If a VCPU returns EXCP_HALTED from the guest code execution and in the mean time receives a work item, it will go to sleep without processing the job. Before sleeping, check if any work has been added. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cpus.c | 2 +- 1 file c

[Qemu-devel] [RFC 09/10] cputlb: Query tlb_flush_page_all

Secure tlb_flush_page_all() by waiting the queried flushes to be actually completed using async_wait_run_on_cpu(); Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 15 ++- include/exec/exec-all.h | 4 ++-- target-arm/helper.c | 4 +

[Qemu-devel] [RFC 07/10] cputlb: Query tlb_flush_by_mmuidx

, we can always get safely the CPUState of the current VCPU without relying on current_cpu. This however complicates a bit the function prototype by adding an argument pointing to the current VCPU's CPUState. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c

[Qemu-devel] [RFC 02/10] softmmu_llsc_template.h: Move to multi-threading

with the new multi-threaded execution. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- softmmu_llsc_template.h | 11 +-- softmmu_template.h | 6 ++ target-arm/op_helper.c | 6 ++ 3 files changed, 21 insertions(+), 2 deletions(-) diff

[Qemu-devel] [RFC 03/10] cpus: Introduce async_wait_run_on_cpu()

and in case process pending work items. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cpus.c| 44 ++-- include/qom/cpu.h | 31 +++ 2 files changed, 73 insertions(+), 2 deletions(-) diff --git a/cp

[Qemu-devel] [RFC 08/10] cputlb: Query tlb_flush_page_by_mmuidx

Similarly to the previous commit, make tlb_flush_page_by_mmuidx query the flushes when targeting different VCPUs. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 90 ++--- include/exec/exec-all.

[Qemu-devel] [RFC 04/10] cputlb: Introduce tlb_flush_other()

-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 28 +++- softmmu_llsc_template.h | 2 +- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/cputlb.c b/cputlb.c index 1586b64..55f7447 100644 --- a/cputlb.c +++ b/cputlb.c @@

[Qemu-devel] [RFC 05/10] target-arm: End TB after ldrex instruction

. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/translate-a64.c | 2 ++ target-arm/translate.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 376cb1c..2a14c14 100644 --- a/target-arm/translate

[Qemu-devel] [RFC 01/10] exec: Introduce tcg_exclusive_{lock, unlock}()

Add tcg_exclusive_{lock,unlock}() functions that will be used for making the emulation of LL and SC instructions thread safe. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cpus.c| 2 ++ exec.c| 18 ++ include/qom/cpu.h | 5 + 3

[Qemu-devel] [RFC 00/10] MTTCG: Slow-path for atomic insns

wpath-for-atomic-v8-mttcg". Alvise Rigo (10): exec: Introduce tcg_exclusive_{lock,unlock}() softmmu_llsc_template.h: Move to multi-threading cpus: Introduce async_wait_run_on_cpu() cputlb: Introduce tlb_flush_other() target-arm: End TB after ldrex instruction cputlb: Add tlb_tables_fl

Re: [Qemu-devel] Any topics for today's MTTCG sync-up call?

Hi Alex, I finally solved the issue I had, the branch is working well as far as I can say. The work I will share, in addition to making the LL/SC work mttcg-aware, extends the various TLB flushes calls with the query-based mechanism: the requesting CPU queries the flushes to the target CPUs and

Re: [Qemu-devel] MTTCG Sync-up call today?

Not from my side. Hope to have some news by the end of the week. Regards, alvise On Mon, May 9, 2016 at 1:56 PM, Alex Bennée wrote: > > Hi, > > Do we have anything we want to discuss today? > > -- > Alex Bennée >

Re: [Qemu-devel] MTTCG Sync-up call today?

Hi Alex, On Mon, Apr 25, 2016 at 11:53 AM, Alex Bennée wrote: > Hi, > > We are due to have a sync-up call today but I don't think I'll be able > to make it thanks to a very rough voice courtesy of my > petri-dishes/children. However since the last call: > > * Posted

[Qemu-devel] [RFC v8 14/14] target-arm: aarch64: Use ls/st exclusive for atomic insns

udio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/helper-a64.c| 55 +++ target-arm/helper-a64.h| 2 + target-arm/translate-a64.c | 168 + target-arm/translate.c | 7 -- 4

[Qemu-devel] [RFC v8 12/14] target-arm: translate: Use ld/st excl for atomic insns

check. In addition, add a simple helper function to emulate the CLREX instruction. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/cpu.h

[Qemu-devel] [RFC v8 13/14] target-arm: cpu64: use custom set_excl hook

for more details). Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/cpu64.c | 8 1 file changed, 8 insertions(+) diff --git a/ta

[Qemu-devel] [RFC v8 11/14] tcg: Create new runtime helpers for excl accesses

..@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- Makefile.target | 2 +- include/exec/helper-gen.h | 3 ++ include/exec/helper-proto.h | 1 + include/exec/helper-tcg.h

[Qemu-devel] [RFC v8 10/14] softmmu: Support MMIO exclusive accesses

CPUs to invalidate the exclusive range in case of collision: basically, it serves the same purpose as TLB_EXCL for the TLBEntries referring exclusive memory. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by:

[Qemu-devel] [RFC v8 06/14] qom: cpu: Add CPUClass hooks for exclusive range

kko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- include/qom/cpu.h | 20 qom/cpu.c | 27 +++ 2 files changed, 47 insertions(+) diff --git a/include/q

[Qemu-devel] [RFC v8 09/14] softmmu: Honor the new exclusive bitmap

<jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c | 36 ++ softmmu_template.h | 65 +

[Qemu-devel] [RFC v8 07/14] softmmu: Add helpers for a new slowpath

udio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 4 ++ include/qom/cpu.h | 5 ++ qom/cpu.c | 2 + softmmu_llsc_template.h | 132 softmmu_template.h | 1

[Qemu-devel] [RFC v8 08/14] softmmu: Add history of excl accesses

Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 21 + exec.c | 19 +++ include/qo

[Qemu-devel] [RFC v8 02/14] softmmu: Simplify helper_*_st_name, wrap unaligned code

ges in probe_write and everything else is identical. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> CC: Alvise Rigo <a.r...@virtualopensystems.com> Signed-off-by: Alex Bennée <alex.ben...@linaro.org> [Alex Bennée: def

[Qemu-devel] [RFC v8 01/14] exec.c: Add new exclusive bitmap to ram_list

starts, the whole memory is set to dirty. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- exec.c | 2 +- include/exec/memory.h

[Qemu-devel] [RFC v8 03/14] softmmu: Simplify helper_*_st_name, wrap MMIO code

ontana <claudio.font...@huawei.com> CC: Alex Bennée <alex.ben...@linaro.org> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- softmmu_template.h | 49 +++-- 1 file changed, 27 insertions(+), 22 deletions(-) diff --gi

[Qemu-devel] [RFC v8 04/14] softmmu: Simplify helper_*_st_name, wrap RAM code

gested-by: Claudio Fontana <claudio.font...@huawei.com> CC: Alex Bennée <alex.ben...@linaro.org> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- softmmu_template.h | 80 +++--- 1 file changed, 40 insertions(+), 40

[Qemu-devel] [RFC v8 05/14] softmmu: Add new TLB_EXCL flag

udio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- include/exec/cpu-all.h | 8 1 file changed, 8 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 83b1781..f8d8feb 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/c

[Qemu-devel] [RFC v8 00/14] Slow-path for atomic instruction translation

the logic in softmmu_template.h and to simplify the methods generation through softmmu_llsc_template.h - Added initial implementation of qemu_{ldlink,stcond}_i32 for tcg/i386 This work has been sponsored by Huawei Technologies Duesseldorf GmbH. Alvise Rigo (14): exec.c: Add new exclusive bitmap

Re: [Qemu-devel] MTTCG Sync-up call today? Agenda items?

Hi Alex, On Mon, Apr 11, 2016 at 1:21 PM, Alex Bennée wrote: > > Hi, > > It's been awhile since we synced-up with quite weeks and Easter out of > the way are we good for a call today? Indeed, it has been a while. > > > Some items I can think would be worth covering: >

Re: [Qemu-devel] [mttcg] cputlb: Use async tlb_flush_by_mmuidx

Hi Paolo, On Mon, Mar 7, 2016 at 10:18 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: > > > On 04/03/2016 15:28, alvise rigo wrote: >> A small update on this. I have a working implementation of the "halted >> state" mechanism for waiting all the pendin

Re: [Qemu-devel] [RFC v7 14/16] target-arm: translate: Use ld/st excl for atomic insns

On Thu, Feb 18, 2016 at 6:02 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Use the new LL/SC runtime helpers to handle the ARM atomic instructions >> in softmmu_llsc_template.h. >> >> I

Re: [Qemu-devel] [RFC v7 10/16] softmmu: Protect MMIO exclusive range

On Thu, Feb 18, 2016 at 5:25 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > alvise rigo <a.r...@virtualopensystems.com> writes: > >> On Wed, Feb 17, 2016 at 7:55 PM, Alex Bennée <alex.ben...@linaro.org> wrote: >>> >>> Alvise Rigo <a.r...@v

Re: [Qemu-devel] [RFC v7 12/16] configure: Use slow-path for atomic only when the softmmu is enabled

On Thu, Feb 18, 2016 at 5:40 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Use the new slow path for atomic instruction translation when the >> softmmu is enabled. >> >> At the moment o

Re: [Qemu-devel] [mttcg] cputlb: Use async tlb_flush_by_mmuidx

(). Is there another better solution? Thank you, alvise On Mon, Feb 29, 2016 at 3:18 PM, alvise rigo <a.r...@virtualopensystems.com> wrote: > I see the risk. I will come back with something and let you know. > > Thank you, > alvise > > On Mon, Feb 29, 2016 at 3:06 PM,

Re: [Qemu-devel] [mttcg] cputlb: Use async tlb_flush_by_mmuidx

I see the risk. I will come back with something and let you know. Thank you, alvise On Mon, Feb 29, 2016 at 3:06 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: > > > On 29/02/2016 15:02, alvise rigo wrote: >> > Yeah, that's the other approach -- really split the thing

Re: [Qemu-devel] [mttcg] cputlb: Use async tlb_flush_by_mmuidx

On Mon, Feb 29, 2016 at 2:55 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 29 February 2016 at 13:50, Paolo Bonzini <pbonz...@redhat.com> wrote: >> >> >> On 29/02/2016 14:21, Peter Maydell wrote: >>> On 29 February 2016 at 13:16, Alvise Rigo

[Qemu-devel] [mttcg] cputlb: Use async tlb_flush_by_mmuidx

to the multi_tcg_v8 branch. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c | 65 1 file changed, 53 insertions(+), 12 deletions(-) diff --git a/cputlb.c b/cputlb.c index 29252d1..1eeeccb 100644 --- a/cputlb.c +++ b/cp

Re: [Qemu-devel] [RFC v7 00/16] Slow-path for atomic instruction translation

On Fri, Feb 19, 2016 at 12:44 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> This is the seventh iteration of the patch series which applies to the >> upstream branch of QEMU (v2.5.0-rc4). >&

Re: [Qemu-devel] [RFC v7 08/16] softmmu: Honor the new exclusive bitmap

On Tue, Feb 16, 2016 at 6:39 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > > > The pages set as exclusive (clean) in the DIRTY_MEMORY_EXCLUSIVE bitmap > > have to have their TLB entries flagged with

Re: [Qemu-devel] [RFC v7 09/16] softmmu: Include MMIO/invalid exclusive accesses

On Tue, Feb 16, 2016 at 6:49 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Enable exclusive accesses when the MMIO/invalid flag is set in the TLB >> entry. >> >> In case a LL access is done

Re: [Qemu-devel] [RFC v7 13/16] softmmu: Add history of excl accesses

On Tue, Feb 16, 2016 at 6:07 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Add a circular buffer to store the hw addresses used in the last >> EXCLUSIVE_HISTORY_LEN exclusive accesses. >> >&

Re: [Qemu-devel] [RFC v7 10/16] softmmu: Protect MMIO exclusive range

On Wed, Feb 17, 2016 at 7:55 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> As for the RAM case, also the MMIO exclusive ranges have to be protected >> by other CPU's accesses. In order to do that, we

Re: [Qemu-devel] [RFC v7 07/16] softmmu: Add helpers for a new slowpath

On Thu, Feb 11, 2016 at 5:33 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> The new helpers rely on the legacy ones to perform the actual read/write. >> >> The LoadLink helper (helper_ldlink_name

Re: [Qemu-devel] [RFC v7 06/16] qom: cpu: Add CPUClass hooks for exclusive range

On Thu, Feb 11, 2016 at 2:22 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> The excl_protected_range is a hwaddr range set by the VCPU at the >> execution of a LoadLink instruction. If a norm

Re: [Qemu-devel] [RFC v7 01/16] exec.c: Add new exclusive bitmap to ram_list

You are right, the for loop with i < DIRTY_MEMORY_NUM works just fine. Thank you, alvise On Thu, Feb 11, 2016 at 2:00 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> The purpose of this new bitm

[Qemu-devel] [RFC v7 01/16] exec.c: Add new exclusive bitmap to ram_list

starts, the whole memory is set to dirty. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- exec.c | 7 +-- include/ex

[Qemu-devel] [RFC v7 14/16] target-arm: translate: Use ld/st excl for atomic insns

check. In addition, add a simple helper function to emulate the CLREX instruction. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/cpu.h

[Qemu-devel] [RFC v7 05/16] softmmu: Add new TLB_EXCL flag

udio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- include/exec/cpu-all.h | 8 1 file changed, 8 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 83b1781..f8d8feb 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/c

[Qemu-devel] [RFC v7 03/16] softmmu: Simplify helper_*_st_name, wrap MMIO code

Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- softmmu_template.h | 66 -- 1 file changed, 44 insertions(+), 22 deleti

[Qemu-devel] [RFC v7 09/16] softmmu: Include MMIO/invalid exclusive accesses

kko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c | 7 +++ softmmu_template.h | 26 -- 2 files changed, 23 insertions(+), 10 deletions(-) diff

[Qemu-devel] [RFC v7 02/16] softmmu: Simplify helper_*_st_name, wrap unaligned code

of the softmmu_helpers. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- softmmu_template.h | 96 ++

[Qemu-devel] [RFC v7 07/16] softmmu: Add helpers for a new slowpath

be a store made by *any* vCPU (although, some implementations allow stores made by the CPU that issued the LoadLink). Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtual

[Qemu-devel] [RFC v7 06/16] qom: cpu: Add CPUClass hooks for exclusive range

kko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- include/qom/cpu.h | 15 +++ qom/cpu.c | 20 2 files changed, 35 insertions(+) diff --git a/include/qom/cpu.h b

[Qemu-devel] [RFC v7 15/16] target-arm: cpu64: use custom set_excl hook

for more details). Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/cpu64.c | 8 1 file changed, 8 insertions(+) diff --git a/ta

[Qemu-devel] [RFC v7 16/16] target-arm: aarch64: add atomic instructions

udio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- configure | 6 +- target-arm/helper-a64.c| 55 +++ target-arm/helper-a64.h| 4 ++ target-arm/op_helper.c | 8 +++ target-arm/tra

[Qemu-devel] [RFC v7 08/16] softmmu: Honor the new exclusive bitmap

gested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c | 44 -- softmmu_template.h | 80 -- 2 files changed, 113 insertion

[Qemu-devel] [RFC v7 11/16] tcg: Create new runtime helpers for excl accesses

..@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- Makefile.target | 2 +- include/exec/helper-gen.h | 3 ++ include/exec/helper-proto.h | 1 + include/exec/helper-tcg.h

[Qemu-devel] [RFC v7 04/16] softmmu: Simplify helper_*_st_name, wrap RAM code

. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- softmmu_template.h | 110 + 1 file changed, 68 insertion

[Qemu-devel] [RFC v7 10/16] softmmu: Protect MMIO exclusive range

range in case of collision. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 20 +--- include/ex

[Qemu-devel] [RFC v7 00/16] Slow-path for atomic instruction translation

by Huawei Technologies Duesseldorf GmbH. Alvise Rigo (16): exec.c: Add new exclusive bitmap to ram_list softmmu: Simplify helper_*_st_name, wrap unaligned code softmmu: Simplify helper_*_st_name, wrap MMIO code softmmu: Simplify helper_*_st_name, wrap RAM code softmmu: Add new TLB_EXCL flag

[Qemu-devel] [RFC v7 12/16] configure: Use slow-path for atomic only when the softmmu is enabled

laudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- configure | 14 ++ 1 file changed, 14 insertions(+) diff --git a/configure b/configure index 44ac9ab..915efcc 100755 --- a/configure +++ b/configure @@ -294,6

[Qemu-devel] [RFC v7 13/16] softmmu: Add history of excl accesses

to forget the EXCL bit set. Suggested-by: Jani Kokkonen <jani.kokko...@huawei.com> Suggested-by: Claudio Fontana <claudio.font...@huawei.com> Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- cputlb.c| 29 +++-- exec.c

Re: [Qemu-devel] Status of my hacks on the MTTCG WIP branch

On Mon, Jan 18, 2016 at 8:09 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > > Alex Bennée <alex.ben...@linaro.org> writes: > > > alvise rigo <a.r...@virtualopensystems.com> writes: > > > >> On Fri, Jan 15, 2016 at 4:25 PM, Alex Bennée <a

Re: [Qemu-devel] [RFC PATCH 2/2] softmmu: simplify helper_*_st_name with smmu_helper(do_unl_store)

On Fri, Jan 8, 2016 at 4:53 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > From: Alvise Rigo <a.r...@virtualopensystems.com> > > Attempting to simplify the helper_*_st_name, wrap the > do_unaligned_access code into an shared inline function. As this also > removes th

[Qemu-devel] [PATCH v2] target-arm: Use the right MMU index in arm_regime_using_lpae_format

indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/helper.c| 12 target-arm/internals.h | 5 +++-- targ

Re: [Qemu-devel] [PATCH] target-arm: fix MMU index in arm_cpu_do_unaligned_access

On Fri, Jan 15, 2016 at 11:04 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 15 January 2016 at 09:59, Alvise Rigo <a.r...@virtualopensystems.com> > wrote: >> arm_regime_using_lpae_format checks whether the LPAE extension is used >> for stage 1 tr

Re: [Qemu-devel] Status of my hacks on the MTTCG WIP branch

This problem could be related to a missing multi-threaded aware translation of the atomic instructions. I'm working on this missing piece, probably the next week I will publish something. Regards, alvise On Fri, Jan 15, 2016 at 3:24 PM, Pranith Kumar wrote: > Hi Alex, > >

Re: [Qemu-devel] Status of my hacks on the MTTCG WIP branch

On Fri, Jan 15, 2016 at 3:51 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > alvise rigo <a.r...@virtualopensystems.com> writes: > >> This problem could be related to a missing multi-threaded aware >> translation of the atomic instructions. >> I'm

Re: [Qemu-devel] Status of my hacks on the MTTCG WIP branch

On Fri, Jan 15, 2016 at 4:25 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > alvise rigo <a.r...@virtualopensystems.com> writes: > >> On Fri, Jan 15, 2016 at 3:51 PM, Alex Bennée <alex.ben...@linaro.org> wrote: >>> >>> alvise rigo <a.r...

[Qemu-devel] [PATCH] target-arm: fix MMU index in arm_cpu_do_unaligned_access

indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo <a.r...@virtualopensystems.com> --- target-arm/helper.c| 8 target-arm/internals.h | 5 +++-- targ

Re: [Qemu-devel] [PATCH v2] target-arm: raise exception on misaligned LDREX operands

Forcing an unaligned LDREX access in aarch32, QEMU fails the following assert: target-arm/helper.c:5921:regime_el: code should not be reached Running this snippet both baremetal and on top of Linux will trigger the problem: static inline int cmpxchg(volatile void *ptr, unsigned int old,

Re: [Qemu-devel] [RFC v6 11/14] softmmu: Simplify helper_*_st_name, wrap MMIO code

On Mon, Jan 11, 2016 at 10:54 AM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Attempting to simplify the helper_*_st_name, wrap the MMIO code into an >> inline function. >> >> Suggeste

Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation

On Thu, Jan 7, 2016 at 11:22 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 7 January 2016 at 10:21, alvise rigo <a.r...@virtualopensystems.com> wrote: >> Hi, >> >> On Wed, Jan 6, 2016 at 7:00 PM, Andrew Baumann >> <andrew.baum...@microsoft.co

Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation

Hi, On Wed, Jan 6, 2016 at 7:00 PM, Andrew Baumann <andrew.baum...@microsoft.com> wrote: > > Hi, > > > From: qemu-devel-bounces+andrew.baumann=microsoft@nongnu.org > > [mailto:qemu-devel- > > bounces+andrew.baumann=microsoft....@nongnu.org] On Behalf Of >

Re: [Qemu-devel] [RFC v6 10/14] softmmu: Simplify helper_*_st_name, wrap unaligned code

On Thu, Jan 7, 2016 at 3:46 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Attempting to simplify the helper_*_st_name, wrap the >> do_unaligned_access code into an inline function. >> Remove

Re: [Qemu-devel] [RFC v6 08/14] target-arm: Add atomic_clear helper for CLREX insn

On Wed, Jan 6, 2016 at 6:13 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Add a simple helper function to emulate the CLREX instruction. > > And now I see ;-) > > I suspect this should be mer

Re: [Qemu-devel] [RFC v6 02/14] softmmu: Add new TLB_EXCL flag

On Tue, Jan 5, 2016 at 5:10 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Add a new TLB flag to force all the accesses made to a page to follow >> the slow-path. >> >> In the case w

Re: [Qemu-devel] [RFC v6 01/14] exec.c: Add new exclusive bitmap to ram_list

On Fri, Dec 18, 2015 at 2:18 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> The purpose of this new bitmap is to flag the memory pages that are in >> the middle of LL/SC operations (after a LL, be

Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation

Hi Alex, On Thu, Dec 17, 2015 at 5:06 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > > > This is the sixth iteration of the patch series which applies to the > > upstream branch of QEMU (v2.5.0-rc3)

Re: [Qemu-devel] [RFC v6 12/14] softmmu: Simplify helper_*_st_name, wrap RAM code

On Thu, Dec 17, 2015 at 5:52 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > > Alvise Rigo <a.r...@virtualopensystems.com> writes: > >> Attempting to simplify the helper_*_st_name, wrap the code relative to a >> RAM access into an inline function. > > This

Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation

Hi Andreas, On Mon, Dec 14, 2015 at 11:09 PM, Andreas Tobler <andre...@fgznet.ch> wrote: > Alvise, > > On 14.12.15 09:41, Alvise Rigo wrote: >> >> This is the sixth iteration of the patch series which applies to the >> upstream branch of QEMU (v2.5.0-rc3). >&

Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation

Hi Paolo, On Mon, Dec 14, 2015 at 11:17 AM, Paolo Bonzini <pbonz...@redhat.com> wrote: > > > On 14/12/2015 11:04, alvise rigo wrote: >> In any case, what I proposed in the mttcg based v5 was: >> - A LL ensures that the TLB_EXCL flag is set on all the CPU's TLB. >&g

Re: [Qemu-devel] [RFC v6 09/14] softmmu: Add history of excl accesses

On Mon, Dec 14, 2015 at 10:35 AM, Paolo Bonzini <pbonz...@redhat.com> wrote: > > > On 14/12/2015 09:41, Alvise Rigo wrote: >> +static inline void excl_history_put_addr(CPUState *cpu, hwaddr addr) >> +{ >> +/* Avoid some overhead if the add

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