into gen_sse; this is obviously intended for development only.
Eventually, everything that follows this switch will be removed,
along with the SSE tables and all that goes along with it.
Cheers,
-Jan
Jan Bobek (18):
target/i386: introduce gen_ld_modrm_* helpers
target/i386: introduce
From: Richard Henderson
Treat this the same as we already do for other rex bits.
Signed-off-by: Richard Henderson
---
target/i386/translate.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index
From: Jan Kiszka
I haven't been doing anything here for a long time, nor does my git repo
still play a role.
Signed-off-by: Jan Kiszka
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d6de200453..238feb965f 100644
--- a/MAINTAINERS
+++ b
On 7/20/19 8:46 PM, Richard Henderson wrote:
> On 7/11/19 3:33 PM, Jan Bobek wrote:
>> +# VEX.256.0F.WIG 28 /r: VMOVAPS ymm1, ymm2/m256
>> +# VEX.256.0F.WIG 29 /r: VMOVAPS ymm2/m256, ymm1
>> +VMOVAPS AVX2 0010100 d \
>> + !constraints { vex($_, m => 0x0F, l
On 7/20/19 8:04 PM, Richard Henderson wrote:
> On 7/11/19 3:32 PM, Jan Bobek wrote:
>> +# VEX.LIG.F3.0F.WIG 10 /r: VMOVSS xmm1, xmm2, xmm3
>> +# VEX.LIG.F3.0F.WIG 10 /r: VMOVSS xmm1, m32
>> +# VEX.LIG.F3.0F.WIG 11 /r: VMOVSS xmm1, xmm2, xmm3
>> +# VEX.LIG.F3.0F.
On 7/20/19 5:19 PM, Richard Henderson wrote:
> On 7/11/19 3:32 PM, Jan Bobek wrote:
>> +# F3 0F 2A /r: CVTSI2SS xmm1,r/m32
>> +CVTSI2SS SSE2 00101010 \
>> + !constraints { rep($_); modrm($_); !(defined $_->{modrm}{reg2} &&
>> $_->{modrm}{reg2}
On 7/20/19 1:50 PM, Richard Henderson wrote:
> On 7/11/19 3:32 PM, Jan Bobek wrote:
>> +# NP 0F F7 /r: MASKMOVQ mm1, mm2
>> +MASKMOVQ SSE 0111 \
>> + !constraints { modrm($_); $_->{modrm}{reg} &= 0b111; $_->{modrm}{reg2} &=
>> 0b111 if defi
On 7/20/19 9:58 PM, Richard Henderson wrote:
> On 7/11/19 3:32 PM, Jan Bobek wrote:
>> +sub load(%)
>> +{
>> +my (%args) = @_;
>> +
>> +@memory_opts{keys %args} = values %args;
>> +$memory_opts{is_write} = 0;
>> +}
On 7/20/19 9:54 PM, Richard Henderson wrote:
> On 7/11/19 3:32 PM, Jan Bobek wrote:
>> +sub data16($%)
>> +{
>> +my ($insn, %data16) = @_;
>> +$insn->{data16} = \%data16;
>> +}
>> +
>> +sub rep($%)
>> +{
>> +my ($insn, %rep)
On 22.07.19 12:31, Liran Alon wrote:
>> On 22 Jul 2019, at 13:20, Jan Kiszka wrote:
>>
>> On 22.07.19 11:44, Liran Alon wrote:
>>>
>>>
>>>> On 22 Jul 2019, at 7:00, Jan Kiszka wrote:
>>>>
>>>> Writing the nested state e.g.
On 22.07.19 11:44, Liran Alon wrote:
>
>
>> On 22 Jul 2019, at 7:00, Jan Kiszka wrote:
>>
>> Writing the nested state e.g. after a vmport access can invalidate
>> important parts of the kernel-internal state, and it is not needed as
>> well. So leave
Writing the nested state e.g. after a vmport access can invalidate
important parts of the kernel-internal state, and it is not needed as
well. So leave this out from KVM_PUT_RUNTIME_STATE.
Suggested-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
---
target/i386/kvm.c | 10 +-
1 file
From: Jan Kiszka
nb_queue was not zeroed so that we no longer delivered events if a
previous guest left the device in an overflow state.
The state of absolute does not matter as the next vmmouse_update_handler
call will align it again.
Signed-off-by: Jan Kiszka
---
hw/i386/vmmouse.c | 1 +
1
On 03.06.19 02:36, Michael S. Tsirkin wrote:
> On Sun, Jun 02, 2019 at 01:42:13PM +0200, Jan Kiszka wrote:
>> From: Jan Kiszka
>>
>> Masked entries will not generate interrupt messages, thus do no need to
>> be routed by KVM. This is a cosmetic cleanup, just avoid
On 7/12/19 9:34 AM, Alex Bennée wrote:
>
> Jan Bobek writes:
>
>> This is v3 of the patch series posted in [1] and [2]. Note that this
>> is the first fully-featured patch series implementing all desired
>> functionality, including (V)LDMXCSR and VSIB-based i
On 7/12/19 10:24 AM, Richard Henderson wrote:
> On 7/12/19 12:32 AM, Jan Bobek wrote:
>> +sub vex($%)
>> +{
>> +my ($insn, %vex) = @_;
>> +my $regidw = $is_x86_64 ? 4 : 3;
>> +
>> +# There is no point in randomizing other VEX fields,
On 7/12/19 10:11 AM, Richard Henderson wrote:
> On 7/12/19 12:32 AM, Jan Bobek wrote:
>> The module risugen_x86_asm.pm exports named register constants and
>> asm_insn_* family of functions, which greatly simplify emission of x86
>> instructions.
>>
On 7/12/19 1:48 AM, Richard Henderson wrote:
> On 7/12/19 12:32 AM, Jan Bobek wrote:
>> insnv allows emitting variable-length instructions in little-endian or
>> big-endian byte order; it subsumes functionality of former insn16()
>> and insn32() functions.
>>
>&
Add AVX instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 1362 ++
1 file changed, 1362 insertions(+)
diff --git a/x86.risu b/x86.risu
index 177979a..03ffc89 100644
--- a/x86.risu
+++ b/x86.risu
@@ -29,6
Add AVX2 instructions to the configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 1239 ++
1 file changed, 1239 insertions(+)
diff --git a/x86.risu b/x86.risu
index 03ffc89..1705a8e 100644
--- a/x86.risu
+++ b/x86.risu
@@ -91,6 +91,12
Add SSE2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 734 +++
1 file changed, 734 insertions(+)
diff --git a/x86.risu b/x86.risu
index 2d963fc..b9d424e 100644
--- a/x86.risu
+++ b/x86.risu
@@ -23,48
Add SSE4.1 and SSE4.2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 270 +++
1 file changed, 270 insertions(+)
diff --git a/x86.risu b/x86.risu
index 6f89a80..bc6636e 100644
--- a/x86.risu
+++ b/x86.risu
The module risugen_x86_constraints.pm provides environment for
evaluating x86 "!constraints" blocks. This is facilitated by the
single exported function eval_constraints_block.
Signed-off-by: Jan Bobek
---
risugen_x86_constraints.pm | 154 +
1 fi
extract_fields can extract named variable fields from an opcode; it
returns a hash which can be then passed as environment parameter to
eval_block. More importantly, this allows the caller to augment the
block environment with more variables, if they wish to do so.
Signed-off-by: Jan Bobek
The module risugen_x86_asm.pm exports named register constants and
asm_insn_* family of functions, which greatly simplify emission of x86
instructions.
Signed-off-by: Jan Bobek
---
risugen_x86_asm.pm | 918 +
1 file changed, 918 insertions(+)
create
valid x86 instructions may be up to 15 bytes long, the
length constraint described above only applies to the main opcode
field, which is usually only 1 or 2 bytes long. Therefore, the primary
purpose of this change is to allow 1-byte x86 opcodes.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
insnv allows emitting variable-length instructions in little-endian or
big-endian byte order; it subsumes functionality of former insn16()
and insn32() functions.
randint can reliably generate signed or unsigned integers of arbitrary
width.
Signed-off-by: Jan Bobek
---
risugen_common.pm | 55
Add SSSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 160 +++
1 file changed, 160 insertions(+)
diff --git a/x86.risu b/x86.risu
index d40b9df..6f89a80 100644
--- a/x86.risu
+++ b/x86.risu
@@ -286,6
; both master and slave modes work
in both 32-bit and 64-bit modes.
Cheers,
-Jan
Changes since v2:
Too many to be listed individually; this patch series might be
better reviewed on its own.
References:
1. https://lists.nongnu.org/archive/html/qemu-devel/2019-06/msg04123.html
2. https
The module risugen_x86_memory.pm provides environment for evaluating
x86 "!memory" blocks. This is facilitated by the single exported
function eval_memory_block.
Signed-off-by: Jan Bobek
---
risugen_x86_memory.pm | 87 +++
1 file changed, 87
risugen_x86.pm is the main backend module for Intel i386 and x86_64
architectures; it orchestrates generation of the test code with
support from the rest of risugen_x86_* modules.
Signed-off-by: Jan Bobek
---
risugen_x86.pm | 518 +
1 file changed
Add SSE instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 318 +++
1 file changed, 318 insertions(+)
diff --git a/x86.risu b/x86.risu
index 208ac16..2d963fc 100644
--- a/x86.risu
+++ b/x86.risu
@@ -35,6
Add AES-NI and PCLMULQDQ instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 45 +
1 file changed, 45 insertions(+)
diff --git a/x86.risu b/x86.risu
index bc6636e..177979a 100644
--- a/x86.risu
+++ b/x86.risu
@@ -886,6
Add SSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 50 ++
1 file changed, 50 insertions(+)
diff --git a/x86.risu b/x86.risu
index b9d424e..d40b9df 100644
--- a/x86.risu
+++ b/x86.risu
@@ -161,6 +161,26
This flag instructs the x86 backend to emit 64-bit (rather than
32-bit) code.
Signed-off-by: Jan Bobek
---
risugen | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/risugen b/risugen
index 0c859aa..50920eb 100755
--- a/risugen
+++ b/risugen
@@ -10,6 +10,7 @@
# Peter
Add an x86 configuration file with all MMX instructions.
Signed-off-by: Jan Bobek
---
x86.risu | 321 +++
1 file changed, 321 insertions(+)
create mode 100644 x86.risu
diff --git a/x86.risu b/x86.risu
new file mode 100644
index 000
to filter out the test instructions using
these registers.
Signed-off-by: Jan Bobek
---
risugen | 13 +
1 file changed, 13 insertions(+)
diff --git a/risugen b/risugen
index 50920eb..76424e1 100755
--- a/risugen
+++ b/risugen
@@ -311,6 +311,9 @@ Valid options:
--sve
On 7/11/19 9:57 AM, Richard Henderson wrote:
> On 7/11/19 3:29 PM, Jan Bobek wrote:
>> However, I downloaded a fresh copy of Intel SDM off the Intel website
>> this morning (just to make sure) and in Volume 2B, Section "4.3
>> Instructions (M-U)," page 4-208 titl
On 7/11/19 2:45 AM, Alex Bennée wrote:
>
> Jan Bobek writes:
>
>> On 7/3/19 6:01 PM, Peter Maydell wrote:
>>> On Mon, 1 Jul 2019 at 05:43, Jan Bobek wrote:
>>>>
>>>> Add an x86 configuration file with all MMX instructions.
>>>>
>
On 7/11/19 5:32 AM, Richard Henderson wrote:
> On 7/10/19 8:29 PM, Jan Bobek wrote:
>>>> +# Arithmetic Instructions
>>>> +PADDB MMX 1100 !emit { modrm(); mem(size =>
>>>> 8); }
>>>> +PADDW MMX
On 7/11/19 5:26 AM, Richard Henderson wrote:
> On 7/10/19 8:21 PM, Jan Bobek wrote:
>> Doesn't B8 (without REX.W) work for x86_64, too? It zeroes the upper
>> part of the destination, so it's effectively zero-extending, and it's
>> one byte shorter than C7 (no ModR/M byte n
On 7/3/19 6:01 PM, Peter Maydell wrote:
> On Mon, 1 Jul 2019 at 05:43, Jan Bobek wrote:
>>
>> Add an x86 configuration file with all MMX instructions.
>>
>> Signed-off-by: Jan Bobek
>
>> --- /dev/nul
On 7/3/19 5:49 PM, Richard Henderson wrote:
> On 7/1/19 6:35 AM, Jan Bobek wrote:
>> +MOVQMMX 011 d 1110 !emit { rex(w => 1); modrm(mod
>> => MOD_DIRECT, rm => ~REG_ESP); }
>> +MOVQ_memMMX 011 d 1110 !emit { rex(w =>
On 7/3/19 5:35 PM, Richard Henderson wrote:
> On 7/1/19 6:35 AM, Jan Bobek wrote:
>> Add an x86 configuration file with all MMX instructions.
>>
>> Signed-off-by: Jan Bobek
>> ---
>> x86.risu | 96
On 7/3/19 12:11 PM, Richard Henderson wrote:
> On 7/1/19 6:35 AM, Jan Bobek wrote:
>> +sub write_mov_rr($$)
>> +{
>> +my ($r1, $r2) = @_;
>> +
>> +my %insn = (opcode => X86OP_MOV,
>> +modrm => {mod => MOD_DIRECT,
On 7/3/19 11:47 AM, Richard Henderson wrote:
> On 7/1/19 6:35 AM, Jan Bobek wrote:
>> +sub parse_emitblock($$)
>> +{
>> +my ($rec, $insn) = @_;
>> +my $insnname = $rec->{name};
>> +my $opcode = $insn->{opcode}{value};
>> +
>> +
On 7/3/19 11:37 AM, Richard Henderson wrote:
> On 7/1/19 6:35 AM, Jan Bobek wrote:
>> +VEX_V_UNUSED => 0b,
>
> I think perhaps this is a mistake. Yes, that's what goes in the field, but
> what goes in the field is ~(logical_value).
>
> While for
:35 AM, Jan Bobek wrote:
>> +while ($bitcur < $bitend) {
>> +my $format;
>> +my $bitlen;
>> +
>> +if ($bitcur + 64 <= $bitend) {
>> +$format = "Q";
>> +$bitlen = 64;
>> +
On 10.07.19 18:34, Paolo Bonzini wrote:
> On 10/07/19 18:08, Jan Kiszka wrote:
>> On 10.07.19 16:40, Paolo Bonzini wrote:
>>> On 08/07/19 20:31, Jan Kiszka wrote:
>>>>> -if (cpu_has_nested_virt(env) && !env->nested_state) {
>>>>> +
On 10.07.19 16:40, Paolo Bonzini wrote:
> On 08/07/19 20:31, Jan Kiszka wrote:
>>> -if (cpu_has_nested_virt(env) && !env->nested_state) {
>>> +if (kvm_enabled() && cpu_has_vmx(env) && !env->nested_state) {
>>>
On 08.07.19 20:31, Jan Kiszka wrote:
>
> On 21.06.19 13:30, Paolo Bonzini wrote:
>> From: Liran Alon
>>
>> Previous commits have added support for migration of nested virtualization
>> workloads. This was done by utilising two new KVM capabil
]
? get_futex_key+0x35d/0x3b0
? do_vfs_ioctl+0x447/0x640
? do_futex+0x157/0x1d0
? ksys_ioctl+0x5e/0x90
? __x64_sys_ioctl+0x16/0x20
? do_syscall_64+0x60/0x120
? entry_SYSCALL_64_after_hwframe+0x49/0xbe
This was on a 5.1.16 distro kernel. Currently rebuilding 5.2 vanilla.
Looks like we have up to two critical bugs here...
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
EXT_VMX) && !vmx_mig_blocker) {
> -error_setg(_mig_blocker,
> - "Nested VMX virtualization does not support live
> migration yet");
> -r = migrate_add_blocker(vmx_mig_blocker, _err);
> +if (cpu_has_nested_virt(env) &
Add SSE4.1 and SSE4.2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 69
1 file changed, 69 insertions(+)
diff --git a/x86.risu b/x86.risu
index 35992d6..a73e209 100644
--- a/x86.risu
+++ b/x86.risu
Add SSE2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 153 +++
1 file changed, 153 insertions(+)
diff --git a/x86.risu b/x86.risu
index c29b210..9b63d6b 100644
--- a/x86.risu
+++ b/x86.risu
@@ -15,179
Add AVX instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 288 +++
1 file changed, 288 insertions(+)
diff --git a/x86.risu b/x86.risu
index 17a5082..d3115ac 100644
--- a/x86.risu
+++ b/x86.risu
@@ -17,452
Add an x86 configuration file with all MMX instructions.
Signed-off-by: Jan Bobek
---
x86.risu | 96
1 file changed, 96 insertions(+)
create mode 100644 x86.risu
diff --git a/x86.risu b/x86.risu
new file mode 100644
index 000
Add SSE instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 100 +++
1 file changed, 100 insertions(+)
diff --git a/x86.risu b/x86.risu
index f2dd9b0..c29b210 100644
--- a/x86.risu
+++ b/x86.risu
@@ -19,6
Add SSSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 38 ++
1 file changed, 38 insertions(+)
diff --git a/x86.risu b/x86.risu
index 01181dd..35992d6 100644
--- a/x86.risu
+++ b/x86.risu
@@ -77,6 +77,13 @@ ADDPD
Add AVX2 instructions to the configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 257 +++
1 file changed, 257 insertions(+)
diff --git a/x86.risu b/x86.risu
index d3115ac..74c4ce8 100644
--- a/x86.risu
+++ b/x86.risu
@@ -33,16 +33,22
valid x86 instructions may be up to 15 bytes long, the
length constraint described above only applies to the main opcode
field, which is usually only 1 or 2 bytes long. Therefore, the primary
purpose of this change is to allow 1-byte x86 opcodes.
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
passed as arguments.
- rand_fill uses randint_constr to fill a given hash with
(optionally constrained) random values.
Signed-off-by: Jan Bobek
---
risugen_common.pm | 107 +++---
1 file changed, 101 insertions(+), 6 deletions(-)
diff --git
Add SSE3 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 14 ++
1 file changed, 14 insertions(+)
diff --git a/x86.risu b/x86.risu
index 9b63d6b..01181dd 100644
--- a/x86.risu
+++ b/x86.risu
@@ -49,6 +49,11 @@ PMOVMSKBSSE2
The risugen_x86.pm module contains most of the code specific to Intel
i386 and x86_64 architectures. This commit also adds --x86_64 option,
which enables emission of 64-bit (rather than 32-bit) assembly.
Signed-off-by: Jan Bobek
---
risugen| 6 +-
risugen_x86.pm | 498
The module risugen_x86_asm.pm exports several constants and the
function write_insn, which work in tandem to allow emission of x86
instructions in more clear and structured manner.
Signed-off-by: Jan Bobek
---
risugen_x86_asm.pm | 252 +
1 file
The helper module risugen_x86_emit.pm exports a single function
"parse_emitblock", which serves to capture and return instruction
constraints described by "emit" blocks in an x86 configuration file.
Signed-off-by: Jan Bobek
---
risugen | 2 +-
risu
/qemu-devel/2019-06/msg06489.html
Jan Bobek (14):
risugen_common: add insnv, randint_constr, rand_fill
risugen_x86_asm: add module
risugen_x86_emit: add module
risugen_x86: add module
risugen: allow all byte-aligned instructions
x86.risu: add MMX instructions
x86.risu: add SSE
From: Jan Kiszka
No reason to deny this type.
Signed-off-by: Jan Kiszka
---
hw/arm/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 431e2900fd..ed009fa447 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -176,6 +176,7 @@ static const int
On 6/27/19 6:29 AM, Richard Henderson wrote:
> On 6/19/19 7:04 AM, Jan Bobek wrote:
>> +sub write_mov_reg_imm($$)
>> +{
>> +my ($reg, $imm) = @_;
>> +
>> +my %insn = (opcode => {value => 0xB8 | ($reg & 0x7), len => 1},
>> +
On 6/27/19 6:53 AM, Richard Henderson wrote:
> On 6/27/19 12:29 PM, Richard Henderson wrote:
>> On 6/19/19 7:04 AM, Jan Bobek wrote:
>>> +--x86_64 : generate 64-bit (rather than 32-bit) x86 code.
>> Better is to use
>>
>> .mode x86.64
>&g
On 6/27/19 5:05 AM, Richard Henderson wrote:
> On 6/19/19 7:04 AM, Jan Bobek wrote:
>> +sub rex_encode(%)
>> +{
>> +my (%args) = @_;
>> +
>> +$args{w} = 0 unless defined $args{w};
>> +$args{r} = 0 unless defined $args{w};
>> +$args{x}
On 6/27/19 4:53 AM, Richard Henderson wrote:
> On 6/19/19 7:04 AM, Jan Bobek wrote:
>> +my $value = ($args{bigendian}
>> + ? ($args{value} >> (8 * $args{len} - $bitlen))
>> + : $args{value});
> ...
>> +$
Add all SSE2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek
---
x86.risu | 160 ---
1 file changed, 153 insertions(+), 7 deletions(-)
diff --git a/x86.risu b/x86.risu
index cc40bbc..b3e4c88 100644
--- a/x86.risu
+++ b
The risugen_x86.pm module contains most of the code specific to Intel
i386 and x86_64 architectures. This commit also adds --x86_64 option,
which enables emission of 64-bit (rather than 32-bit) assembly.
Signed-off-by: Jan Bobek
---
risugen| 6 +-
risugen_x86.pm | 455
specify constraints on memory contents. However, this patch
series should have enough code to demonstrate my intended general
approach, and that's what I am looking for feedback for.
Best,
-Jan
Jan Bobek (7):
risugen_common: add insnv, randint_constr, rand_fill
risugen_x86_asm: add module
risugen_
valid x86 instructions may be up to 15 bytes long, the
length constraint described above only applies to the main opcode
field, which is usually only 1 or 2 bytes long. Therefore, the primary
purpose of this change is to allow 1-byte x86 opcodes.
Signed-off-by: Jan Bobek
---
risugen | 7 +++
1
passed as arguments.
- rand_fill uses randint_constr to fill a given hash with
(optionally constrained) random values.
Signed-off-by: Jan Bobek
---
risugen_common.pm | 101 +++---
1 file changed, 95 insertions(+), 6 deletions(-)
diff --git
The module risugen_x86_asm.pm exports several constants and the
function write_insn, which work in tandem to allow emission of x86
instructions in more clear and structured manner.
Signed-off-by: Jan Bobek
---
risugen_x86_asm.pm | 186 +
1 file
Add an x86 configuration file with all SSE instructions.
Signed-off-by: Jan Bobek
---
x86.risu | 99
1 file changed, 99 insertions(+)
create mode 100644 x86.risu
diff --git a/x86.risu b/x86.risu
new file mode 100644
index 000
The helper module risugen_x86_emit.pm exports a single function
"parse_emitblock", which serves to capture and return instruction
constraints described by "emit" blocks in an x86 configuration file.
Signed-off-by: Jan Bobek
---
risugen | 2 +-
risu
On 02.06.19 14:10, Peter Xu wrote:
On Sun, Jun 02, 2019 at 01:42:13PM +0200, Jan Kiszka wrote:
From: Jan Kiszka
Masked entries will not generate interrupt messages, thus do no need to
be routed by KVM. This is a cosmetic cleanup, just avoiding warnings of
the kind
qemu-system-x86_64
From: Jan Kiszka
Masked entries will not generate interrupt messages, thus do no need to
be routed by KVM. This is a cosmetic cleanup, just avoiding warnings of
the kind
qemu-system-x86_64: vtd_irte_get: detected non-present IRTE (index=0,
high=0xff00, low=0x100)
if the masked entry happens
From: Richard Henderson
The state expected for a given test must be specifically requested
with the --xfeatures=mask command-line argument. This is recorded
with the saved state so that it is obvious if the apprentice is given
a different argument. Any features beyond what are present on the
Have the --xfeatures option accept "sse", "avx" and "avx512" in
addition to a plain numerical value, purely for users' convenience.
Don't fail silently when an incorrect value is specified, to avoid
confusion.
Suggested-by: Richard Henderson
Signed-off-by: Jan B
This allows us to drop dependency on NASM and build the test image
with GCC only. Adds support for x86_64, too.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
Makefile| 3 +++
test_i386.S | 41
The original code used "magic numbers", which made it unclear in
some places. Include a reference to the Intel manual where the
constants' meaning is discussed.
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
risu_reginfo_i
at
it, expand the support to x86_64 as well.
Suggested-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
risu_reginfo_i386.h | 24
risu_reginfo_i386.c | 147 ++--
2 files changed, 127
y: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
risu_i386.c | 35 ++-
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/risu_i386.c b/risu_i386.c
index 2d2f325..06d95e5 100644
--- a/risu_i3
-by: Jan Bobek
---
risu_reginfo_i386.h | 37 +
risu_i386.c | 23 +--
2 files changed, 38 insertions(+), 22 deletions(-)
create mode 100644 risu_reginfo_i386.h
diff --git a/risu_reginfo_i386.h b/risu_reginfo_i386.h
new file mode
Now that i386 and x86_64 architectures are supported by RISU, we want
to detect them and build RISU for them automatically.
Suggested-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
configure | 10 ++
1 file changed, 6
-by: Jan Bobek
---
risu_i386.c | 54 ---
risu_reginfo_i386.c | 68 +
2 files changed, 68 insertions(+), 54 deletions(-)
create mode 100644 risu_reginfo_i386.c
diff --git a/risu_i386.c b/risu_i386.c
index 6798a78
y: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 4aad448..b362dbe 100644
--- a/Makefile
+++ b/Makefile
@@ -17,7 +17,7 @@ VPATH=$(SRC
The code being removed is a remnant of the past implementation; it has
since been replaced by its more powerful, architecture-independent
counterpart in reginfo.c.
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Signed-off-by: Jan Bobek
---
risu_i386.c | 58
/2019-05/msg04922.html
4. https://lists.nongnu.org/archive/html/qemu-devel/2019-05/msg04903.html
Jan Bobek (10):
Makefile: undefine the arch name symbol
risu_i386: move reginfo_t and related defines to risu_reginfo_i386.h
risu_i386: move reginfo-related code to risu_reginfo_i386.c
ted, i.e. the AVX state
is included even though it has been set to all zeros via vxorps,
3. the AVX state can be brought back to the initial configuration via
XRSTOR with the AVX component removed.
Cheers,
-Jan
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Description: OpenPGP digital signature
On 5/21/19 12:56 PM, Richard Henderson wrote:
> On 5/21/19 12:48 PM, Jan Bobek wrote:
>> I get the same behavior, but it only occurs on 32bit builds of
>> RISU. Specifically, in risu_reginfo_i386.c, lines 172--178:
>>
>> for (i = 0; i < nvecregs; ++i) {
>>
t; Are
>> you trying to run the test as seen in patch 7 against the final
>> series?
>
> Running against:
>
> commit 555748b35849ad4d354a9a3cd7f8549994b2bea4 (HEAD ->
> review/i386-support-v2)
> Author: Jan Bobek
> Date: Fri May 17 18:44:50 2019 -0400
>
>
assertion would fail. I guess there's a point to be made about
release builds, in which the assert may have been optimized out; shall
I turn it into an error message instead?
> However the series is looking pretty good so far. Looking forward to the
> next iteration.
Once again, than
From: Richard Henderson
The state expected for a given test must be specifically requested
with the --xfeatures=mask command-line argument. This is recorded
with the saved state so that it is obvious if the apprentice is given
a different argument. Any features beyond what are present on the
Have the --xfeature option accept "sse", "avx" and "avx512" in
addition to a plain numerical value, purely for users' convenience.
Suggested-by: Richard Henderson
Signed-off-by: Jan Bobek
---
risu_reginfo_i386.c | 11 ++-
1 file changed, 10 insertions
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