Re:Re: Re: how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?

Hi peter: i see, much, much helpfull. thank you! :). At 2024-04-09 18:51:26, "Peter Maydell" wrote: >On Tue, 9 Apr 2024 at 11:40, tugouxp <13824125...@163.com> wrote: >> ===>yes, i somehow a little bit of guess such like that, but when try to >> find some

Re:Re: how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?

u offer me the demo code position of do the sync like "pause execution of all the other guest vCPU threads,", to make the atomic operations meet the sematics? thank you! BRs zlcao. At 2024-04-09 18:10:42, "Peter Maydell" wrote: >On Tue, 9 Apr 2024 at 10:58, tugoux

how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?

Hi folks: How does the qemu emulate the target that support "atomic" ISA, such as riscv "amo" instruction on host machine that does NOT support atomic instructions ? is this scenario happends? thank you! BRs zlcao.

Re:Re: What this mean "dead: 1" and "dead: 0 1" on each tb block start?

So, flag is also the paramter index right? ,what about the sync ? At 2020-07-30 00:16:25, "Richard Henderson" wrote: >On 7/29/20 7:27 AM, tugouxp wrote: >> HI folks: >> on each tb block start, there are following ir code, and the most confusing &

What this mean "dead: 1" and "dead: 0 1" on each tb block start?

HI folks: on each tb block start, there are following ir code, and the most confusing me is that the postfix of each line "dead:" flag, what it is represent precisely? i guess it may be related to the register or varible liveness for help generating tghe target machine code, but i cant get

What is this mean of the comment?

Hi folks: in flollowing comment of tcg.h, it says every helper max need 6 input argument and 1 output argument, but why here both multiply by 2 in here? what is the 14 mean? thank you! 520 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, 521this

What is the "E10, E20_0 XXX" Flag means on arm port?

Hi folks: I Know the arm prelidge level can be divieded into EL0, EL1, EL2 and EL3, but i am confused by the following definition on qemu arm port. for example, why E10 are postfix with _0 and _1, what is this meansings? typedef enum ARMMMUIdx { 2879 /* 2880 ¦* A-profile. 2881

what is the difference to transfer elf execute file or binary file on "-kernel" paramter?

what is the difference to transfer elf execute file or binary file on "-kernel" paramter? is it the same and all be reconganized rightly for qemu? thank you!

what is the symbole "leul" mean on this code?

HI guys: i am stucked by the following code,and i can find document illustrations this nowhere. what does the "leul" stands for? and the postfix 10 means what？ thank you! 10 6001 11 movi_i32 tmp3,$0x60010020pref=all 12

according what does the qemu know to exit current TB and find helper functions from environment?

Hi folks: a questions puzzles me during review the qemu code of 5.0.0, take vexpress emulation arm A9 on RTOS for example. the emulated RTOS has its own "printf" implementations, so during the qemu emulations, it would find helper_le_stl_mmu() store_helper()

Re:Re: Is qemu could be a "FSM" state machine if running on a "quiet and clean" host pc without random event input?

Thank you, much appreciate your thought and meaningful for me! At 2020-05-14 07:22:12, "John Snow" wrote: > > >On 5/11/20 10:07 AM, tugouxp wrote: >> Hi folks: >> i want to know about whether therr are limitations during qemu >> emulation

Is qemu could be a "FSM" state machine if running on a "quiet and clean" host pc without random event input?

Hi folks: i want to know about whether therr are limitations during qemu emulation systems, for exampe, did the regular bugs corener case cant be duplicated on qeme but exist on real boads? why thing this is that , i have ever use hdl simulator (modsim and iverilog) and openrisc processor

is there any way to make qemu stop at the very first instruction of the emulation process and wait for gdb connect?

is there any way to make qemu stop at the very first instruction of the emulation process and wait for gdb connect? for i want to know the boot sequence of the first instrction of the target system, how to get this? thank you .

Is there anyway to get the emulation rates MIPS (instructions in a period, not mips cpu) of qemu?

HI folks: I need to get the mips ovulation about the X86 host emulated arm32 platform, so Is there anyway to get the emulation rates MIPS (instructions in a period, not mips cpu) of qemu? thank you

Re: [Qemu-devel] what is the behavier precisely if a tb was interrupted by a interrupt or signal?

thank you. if so ,the interrupt granularity cant be instructions precisely, but tb precisely, for qemu cant check the interrupt at each instructions execution stage, right? At 2018-12-24 21:49:07, "Peter Maydell" wrote: >On Mon, 24 Dec 2018 at 10:11, tugouxp <138

[Qemu-devel] what is the behavier precisely if a tb was interrupted by a interrupt or signal?

hi folks: think about the scenario like that, a tb block contain 9 native instructions execute sequentially if a interrupt or a signal happens before instruction 6 executed, did the tb be finished before response to the interrupt or the exited at once to response the interrupt?

Re: [Qemu-devel] did the qemu can emulate the whole system with the processor that without support the "virtulization and kvm"?

t 2018-12-21 22:14:58, "Alex Bennée" wrote: > >tugouxp <13824125...@163.com> writes: > >> thank you. >> >> i just want to confirm one thing, that is whether the qemu can emulate a >> whole operation system just by analysis instructions by instruc

Re: [Qemu-devel] did the qemu can emulate the whole system with the processor that without support the "virtulization and kvm"?

17:01:02, "Alex Bennée" wrote: > >tugouxp <13824125...@163.com> writes: > >> Hi alex: >> now my host machine did not have the "/dev/kvm" nodes and no chance to >> make it exists. >> so i want to know whether the "/dev/kvm"

Re: [Qemu-devel] is the "tcg translation" necessary when the "kvm acceleration" emulation mode enabled?

in this scenario, the host and target arch is not the >> same, so how to use the "kvm mechainsim" in this case? so the >> instructions feed to the kvm module to run must be translated By TCG >> module? right? > >KVM cannot be used in this case; KVM is only enabled when the

[Qemu-devel] is the "tcg translation" necessary when the "kvm acceleration" emulation mode enabled?

hi folks: i am very puzzled about the relationship between "target cpu instruction" translated to host instructions through TCG module and the "kvm" acceleration" mode. think about three scenario of emulation: scenario 1, 2 and 3 as follows: 1. target cpu: x86_64, host cpu:

Re: [Qemu-devel] did the qemu can emulate the whole system with the processor that without support the "virtulization and kvm"?

nks for your support.! At 2018-12-20 20:31:09, "Alex Bennée" wrote: > >tugouxp <13824125...@163.com> writes: > >> hi folks: >> did the qemu can emulate the whole system(such as ubuntu) with >> the processor that without support the "vi

[Qemu-devel] did the qemu can emulate the whole system with the processor that without support the "virtulization and kvm"?

hi folks: did the qemu can emulate the whole system(such as ubuntu) with the processor that without support the "virtulization and kvm"? thanks for your kindly support.

[Qemu-devel] how to get the "intermediate tcg" string output to debug qemu?

hi folks: i want to get the translated tcg operations printed on my test pattern, so is there any way to get this for convenient? thanks for your kindley help.

[Qemu-devel] how to get the "intermediate tcg" string output to debug qemu?

hi folks: i want to get the translated tcg operations printed on my test pattern, so is there any way to get this for convenient? thanks for your kindley help.