Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

2021-04-14 Thread Alistair Francis
On Thu, Apr 15, 2021 at 2:18 PM LIU Zhiwei wrote: > > Hi Alistair, > > I think that this bug has been resolved in my packed-extension patch set[1]. > > Would you mind to have a test and merge it before the whole patch set? Great! Thanks I have applied patch 3 for the next PR. Alistair > >

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

2021-04-14 Thread LIU Zhiwei
Hi Alistair, I think that this bug has been resolved in my packed-extension patch set[1]. Would you mind to have a test and merge it before the whole patch set? Thanks. Best Regards, Zhiwei [1]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg782125.html On 2021/4/15 上午11:57,

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

2021-04-14 Thread Kito Cheng
Add Frank, he is the SiFive's qemu maintainer. On Thu, Apr 15, 2021 at 11:57 AM Alistair Francis wrote: > > + LIU Zhiwei and Kito Cheng > > Alistair > > On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote: > > > > Public bug reported: > > > > I noticed doing a negate ( 0

Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

2021-04-14 Thread Alistair Francis
+ LIU Zhiwei and Kito Cheng Alistair On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923...@bugs.launchpad.net> wrote: > > Public bug reported: > > I noticed doing a negate ( 0 – 0x8000 ) using vssub.vv produces an > incorrect result of 0x8000 (should saturate to 0x7FFF). > > Here is the

[Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

2021-04-13 Thread Tony Cole
Public bug reported: I noticed doing a negate ( 0 – 0x8000 ) using vssub.vv produces an incorrect result of 0x8000 (should saturate to 0x7FFF). Here is the bit of the code: vmv.v.i v16, 0 … 8f040457vssub.vvv8,v16,v8 I believe