Re: [PATCH] gdb: riscv: Add target description

2020-12-29 Thread Bin Meng
On Wed, Dec 30, 2020 at 3:42 PM Sylvain Pelissier wrote: > > Target description is not currently implemented in RISC-V architecture. Thus > GDB won't set it properly when attached. The patch implements the target > description response. > > Signed-off-by: Sylvain Pelissier > --- >

Re: [PATCH] gdb: riscv: Add target description

2020-12-29 Thread Sylvain Pelissier
Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git

Re: [PATCH] gdb: riscv: Add target description

2020-12-29 Thread Bin Meng
Hi Sylvain, On Wed, Dec 30, 2020 at 12:37 AM Sylvain Pelissier wrote: > > Thank you for your remark here is the new patch: This should not be put into the commit message. Previous commit message is missing. > > Signed-off-by: Sylvain Pelissier > --- > target/riscv/cpu.c | 13 + >

Re: [PATCH] gdb: riscv: Add target description

2020-12-29 Thread Sylvain Pelissier
Thank you for your remark here is the new patch: Signed-off-by: Sylvain Pelissier --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..ed4971978b 100644 --- a/target/riscv/cpu.c +++

Re: [PATCH] gdb: riscv: Add target description

2020-12-28 Thread Bin Meng
On Thu, Dec 24, 2020 at 1:09 AM Sylvain Pelissier wrote: > > Target description is not currently implemented in RISC-V architecture. Thus > GDB won't set it properly when attached. The patch implements the target > description response. > > Signed-off-by: Sylvain Pelissier > --- >

[PATCH] gdb: riscv: Add target description

2020-12-23 Thread Sylvain Pelissier
Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier --- target/riscv/cpu.c | 10 ++ 1 file changed, 10 insertions(+) diff --git