On 10/10/22 02:49, Peter Maydell wrote:
On Sat, 8 Oct 2022 at 16:38, Richard Henderson
wrote:
Intel has now given guarantees about the atomicity of SSE read
and write instructions on cpus supporting AVX. We can use these
instead of the much slower cmpxchg16b.
Derived from
On Sat, 8 Oct 2022 at 16:38, Richard Henderson
wrote:
>
> Intel has now given guarantees about the atomicity of SSE read
> and write instructions on cpus supporting AVX. We can use these
> instead of the much slower cmpxchg16b.
>
> Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
On 10/8/22 08:36, Richard Henderson wrote:
Intel has now given guarantees about the atomicity of SSE read
and write instructions on cpus supporting AVX. We can use these
instead of the much slower cmpxchg16b.
Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
Signed-off-by:
Intel has now given guarantees about the atomicity of SSE read
and write instructions on cpus supporting AVX. We can use these
instead of the much slower cmpxchg16b.
Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
Signed-off-by: Richard Henderson
---
Paolo, we probably ought
