Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

Hi Alistair, On 2022/03/28 8:29, Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI > wrote: >> >> Some bits in RISC-V `misa' CSR should not be reflected in the ISA >> string. For instance, `S' and `U' (represents existence of supervisor >> and user mode, respectively) in

Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

On Mon, Mar 28, 2022 at 7:30 AM Alistair Francis wrote: > On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI > wrote: > > > > Some bits in RISC-V `misa' CSR should not be reflected in the ISA > > string. For instance, `S' and `U' (represents existence of supervisor > > and user mode, respectively) in

Re: [PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

On Sat, Mar 26, 2022 at 3:46 PM Tsukasa OI wrote: > > Some bits in RISC-V `misa' CSR should not be reflected in the ISA > string. For instance, `S' and `U' (represents existence of supervisor > and user mode, respectively) in `misa' CSR must not be copied since > neither `S' nor `U' are valid

[PATCH (PING) 1/1] target/riscv: misa to ISA string conversion fix

Some bits in RISC-V `misa' CSR should not be reflected in the ISA string. For instance, `S' and `U' (represents existence of supervisor and user mode, respectively) in `misa' CSR must not be copied since neither `S' nor `U' are valid single-letter extensions. This commit restricts which bits to