Re: [PATCH 0/2] Risc-V CPU state by hart ID

On Thu, 02 Mar 2023 22:50:53 PST (-0800), mchit...@ventanamicro.com wrote: Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the contiguous logical CPU ID to fetch per CPU state. This patchset

[PATCH 0/2] Risc-V CPU state by hart ID

Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the contiguous logical CPU ID to fetch per CPU state. This patchset implements cpu_by_arch_id for Risc-V to get the CPU state by hart ID which may be