On Wed, Jul 8, 2020 at 5:19 PM Richard Henderson
wrote:
> Do I read that right,
[...]
> means that if DFP is present, float64 has use_first_nan, but float32 does
> not?!?
That's correct. And float64 madd.d/msub.d again don't have it.
> What in the world is going on?
My thoughts exactly. What
On 7/8/20 10:37 AM, Max Filippov wrote:
> On Wed, Jul 8, 2020 at 9:25 AM Richard Henderson
> wrote:
>>
>> On 7/6/20 4:47 PM, Max Filippov wrote:
>>> +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
>>> +{
>>> +set_use_first_nan(true, >fp_status);
>>> +return
On Wed, Jul 8, 2020 at 9:25 AM Richard Henderson
wrote:
>
> On 7/6/20 4:47 PM, Max Filippov wrote:
> > +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
> > +{
> > +set_use_first_nan(true, >fp_status);
> > +return float64_add(a, b, >fp_status);
> > +}
> > +
> > float32
On 7/6/20 4:47 PM, Max Filippov wrote:
> +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
> +{
> +set_use_first_nan(true, >fp_status);
> +return float64_add(a, b, >fp_status);
> +}
> +
> float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
> {
> +
DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA
does not specify how single-precision values are stored in 64-bit
registers. Existing implementations store them in the low half of the
registers.
Add value extraction and write back to single-precision opcodes.
Add new double
