On 12/07/2023 20:11, John Allen wrote:
> On Fri, Jul 07, 2023 at 04:25:22PM +0200, Paolo Bonzini wrote:
>> On 7/6/23 21:40, John Allen wrote:
>>> case 0x8007:
>>> *eax = 0;
>>> -*ebx = 0;
>>> +*ebx = env->features[FEAT_8000_0007_EBX] |
>>>
On Fri, Jul 07, 2023 at 04:25:22PM +0200, Paolo Bonzini wrote:
> On 7/6/23 21:40, John Allen wrote:
> > case 0x8007:
> > *eax = 0;
> > -*ebx = 0;
> > +*ebx = env->features[FEAT_8000_0007_EBX] |
> > CPUID_8000_0007_EBX_SUCCOR;
> > *ecx = 0;
> >
On 7/6/23 21:40, John Allen wrote:
case 0x8007:
*eax = 0;
-*ebx = 0;
+*ebx = env->features[FEAT_8000_0007_EBX] | CPUID_8000_0007_EBX_SUCCOR;
*ecx = 0;
*edx = env->features[FEAT_8000_0007_EDX];
break;
I agree that it needs no
+x86 qemu folks
On 06/07/2023 21:22, Moger, Babu wrote:
> Hi John,
> Thanks for the patches. Few comments below.
>
> On 7/6/23 14:40, John Allen wrote:
>> Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required
>> to
>> be exposed to guests to allow them to handle machine
Hi John,
Thanks for the patches. Few comments below.
On 7/6/23 14:40, John Allen wrote:
> Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required to
> be exposed to guests to allow them to handle machine check exceptions on AMD
> hosts.
>
> Reported-by: William Roche
>
Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required to
be exposed to guests to allow them to handle machine check exceptions on AMD
hosts.
Reported-by: William Roche
Signed-off-by: John Allen
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 4
2 files changed, 5
