Re: [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

On Wed, Dec 29, 2021 at 12:48 PM wrote: > > From: Frank Chang > > Vector single-width floating-point reduction operations for EEW=32 are > supported for Zve32f extension. > > Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc |

[PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

From: Frank Chang Vector single-width floating-point reduction operations for EEW=32 are supported for Zve32f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc