On 5/21/21 3:25 PM, Bin Meng wrote:
> On Fri, May 21, 2021 at 8:46 PM Philippe Mathieu-Daudé
> wrote:
>>
>> On 5/21/21 4:42 AM, Bin Meng wrote:
>>> From: Ruimei Yan
>>>
>>> Per xHCI spec v1.2 chapter 4.17.5 page 296:
>>>
>>> If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP)
>>>
On Fri, May 21, 2021 at 8:46 PM Philippe Mathieu-Daudé
wrote:
>
> On 5/21/21 4:42 AM, Bin Meng wrote:
> > From: Ruimei Yan
> >
> > Per xHCI spec v1.2 chapter 4.17.5 page 296:
> >
> > If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP)
> > shall be cleared automatically when the
On 5/21/21 4:42 AM, Bin Meng wrote:
> From: Ruimei Yan
>
> Per xHCI spec v1.2 chapter 4.17.5 page 296:
>
> If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP)
> shall be cleared automatically when the PCI dword write generated
> by the interrupt assertion is complete.
>
>
From: Ruimei Yan
Per xHCI spec v1.2 chapter 4.17.5 page 296:
If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP)
shall be cleared automatically when the PCI dword write generated
by the interrupt assertion is complete.
Currently QEMU does not clear the IP flag in the MSI /