Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Hi Tyler, Thanks for the explanation. I understand the issue here. I think we should align the priority base in each RISC-V platform to the same value (no matter 0x0 or 0x4) if they use PLIC in the same way. Thanks, Jim Shu On Tue, Sep 27, 2022 at 4:04 AM Tyler Ng wrote: > > Hi Jim, > > Thanks

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Hi Jim, Thanks for raising this comment. I think I understand where the confusion happens and it's because in the OpenTitan machine (which uses the sifive plic), it uses 0x00 as the priority base by default, which was the source of the problems. I'll drop this commit in the next version. -Tyler

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Hi Tyler, This fix is incorrect. In PLIC spec, Interrupt Source Priority Memory Map is 0x00: Reserved (interrupt source 0 does not exist) 0x04: Interrupt source 1 priority 0x08: Interrupt source 2 priority Current RISC-V machines (virt, sifive_u) use 0x4 as priority_base, so current

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Here's the patch SHA that introduced the offset: 0feb4a7129eb4f120c75849ddc9e50495c50cb63 -Tyler On Mon, Sep 5, 2022 at 6:15 AM Andrew Jones wrote: > On Thu, Sep 01, 2022 at 03:50:06PM -0700, Tyler Ng wrote: > > Fixes a bug in which the index of the interrupt priority is off by 1. > > For examp

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

On 2/9/22 00:50, Tyler Ng wrote: Fixes a bug in which the index of the interrupt priority is off by 1. For example, using an IRQ number of 3 with a priority of 1 is supposed to set plic->source_priority[2] = 1, but instead it sets plic->source_priority[3] = 1. When an interrupt is claimed to be s

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

On Thu, Sep 01, 2022 at 03:50:06PM -0700, Tyler Ng wrote: > Fixes a bug in which the index of the interrupt priority is off by 1. > For example, using an IRQ number of 3 with a priority of 1 is supposed to set > plic->source_priority[2] = 1, but instead it sets > plic->source_priority[3] = 1. When

[PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Fixes a bug in which the index of the interrupt priority is off by 1. For example, using an IRQ number of 3 with a priority of 1 is supposed to set plic->source_priority[2] = 1, but instead it sets plic->source_priority[3] = 1. When an interrupt is claimed to be serviced, it checks the index 2 inst