Re: [PATCH 4/5] target/riscv: Add V extention state description

On 9/28/20 9:03 PM, Yifei Jiang wrote: > In the case of supporting V extention, add V extention description > to vmstate_riscv_cpu. > > Signed-off-by: Yifei Jiang > Signed-off-by: Yipeng Yin > --- > target/riscv/machine.c | 25 + > 1 file changed, 25 insertions(+)

[PATCH 4/5] target/riscv: Add V extention state description

In the case of supporting V extention, add V extention description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/machine.c | 25 + 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c