Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread liweiwei
On 2023/3/28 11:31, Richard Henderson wrote: On 3/27/23 18:55, liweiwei wrote: On 2023/3/28 02:04, Richard Henderson wrote: On 3/27/23 03:00, Weiwei Li wrote: @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,   qemu_log_mask(CPU_LOG_MMU, "%s ad %" VAD

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread Richard Henderson
On 3/27/23 18:55, liweiwei wrote: On 2023/3/28 02:04, Richard Henderson wrote: On 3/27/23 03:00, Weiwei Li wrote: @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,   qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread liweiwei
On 2023/3/28 10:31, LIU Zhiwei wrote: On 2023/3/28 9:55, liweiwei wrote: On 2023/3/28 02:04, Richard Henderson wrote: On 3/27/23 03:00, Weiwei Li wrote: @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,   qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRI

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread LIU Zhiwei
On 2023/3/28 9:55, liweiwei wrote: On 2023/3/28 02:04, Richard Henderson wrote: On 3/27/23 03:00, Weiwei Li wrote: @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,   qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread liweiwei
On 2023/3/28 02:04, Richard Henderson wrote: On 3/27/23 03:00, Weiwei Li wrote: @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,   qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",     __func__, address, access_typ

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread Richard Henderson
On 3/27/23 03:00, Weiwei Li wrote: @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); +if (access_type == MMU_INST_

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread Daniel Henrique Barboza
On 3/27/23 07:00, Weiwei Li wrote: Transform the fetch address before page walk when pointer mask is enabled for instruction fetch. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu.h| 1 + target/riscv/cpu_helpe

Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread Daniel Henrique Barboza
On 3/27/23 07:00, Weiwei Li wrote: Transform the fetch address before page walk when pointer mask is enabled for instruction fetch. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu.h| 1 + target/riscv/cpu_helpe

[PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

2023-03-27 Thread Weiwei Li
Transform the fetch address before page walk when pointer mask is enabled for instruction fetch. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 25 +++-- target/riscv/csr.c| 2 -- 3 files chang