Re: [PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64

Thx On Wed, Sep 25, 2019 at 5:58 PM Bin Meng wrote: > > On Wed, Sep 25, 2019 at 5:21 PM wrote: > > > > From: Guo Ren > > > > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we > > need to ignore them. They cannot be a part of ppn. > > > > 1: The RISC-V Instruction Set

Re: [PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64

On Wed, Sep 25, 2019 at 5:21 PM wrote: > > From: Guo Ren > > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we > need to ignore them. They cannot be a part of ppn. > > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture >4.4 Sv39: Page-Based 39-bit

[PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64

From: Guo Ren Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit