Hi, Richard,
On Wed, Sep 16, 2020 at 11:15 PM Richard Henderson
wrote:
>
> On 9/15/20 7:12 PM, Huacai Chen wrote:
> > +case OPC_GSLQ:
> > +gen_base_offset_addr(ctx, t0, rs, lsq_offset);
> > +tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
> > +
On 9/15/20 7:12 PM, Huacai Chen wrote:
> +case OPC_GSLQ:
> +gen_base_offset_addr(ctx, t0, rs, lsq_offset);
> +tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
> +ctx->default_tcg_memop_mask);
> +gen_store_gpr(t0, rt);
> +
Hi, Philippe,
On Wed, Sep 16, 2020 at 3:46 AM Philippe Mathieu-Daudé wrote:
>
> On 9/16/20 4:12 AM, Huacai Chen wrote:
> > From: Jiaxun Yang
> >
> > LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
> > as "load/store quad word" and "shifted load/store" groups of
> > instructions.
> >
On 9/16/20 4:12 AM, Huacai Chen wrote:
> From: Jiaxun Yang
>
> LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
> as "load/store quad word" and "shifted load/store" groups of
> instructions.
>
> This patch add implementation of these instructions:
> gslq: load 16 bytes to GPR
> gssq:
From: Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
