Re: [PATCH v1 1/6] riscv/sifive_u: Add L2-LIM cache memory

On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis wrote: > > On reset only a single L2 cache way is enabled, the others are exposed > as memory that can be used by early boot firmware. This L2 region is > generally disabled using the WayEnable register at a later stage in the > boot process. To

[PATCH v1 1/6] riscv/sifive_u: Add L2-LIM cache memory

On reset only a single L2 cache way is enabled, the others are exposed as memory that can be used by early boot firmware. This L2 region is generally disabled using the WayEnable register at a later stage in the boot process. To allow firmware to target QEMU and the HiFive Unleashed let's add the