On 3/7/24 13:54, Stefan Berger wrote:
On 2/7/24 11:08, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device and an ADC
controller.
All SPI function control is mapped into the SPI register s
On 3/7/24 13:54, Stefan Berger wrote:
On 2/7/24 11:08, Chalapathi V wrote:
+#define COUNTER_CONFIG_REG_SHIFT_COUNT_N1 PPC_BITMASK(0 , 7)
No space before the ',' ==> PPC_BITMASK(0, 7)
On 2/7/24 11:08, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. In this commit SPI configuration component i
