Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting

2020-01-10 Thread Palmer Dabbelt
On Wed, 08 Jan 2020 18:33:40 PST (-0800), richard.hender...@linaro.org wrote: On 1/9/20 11:49 AM, Palmer Dabbelt wrote: +    irqs = (pending & ~env->mideleg & -mie) | (pending &  env->mideleg & -sie); Isn't "-unsigned" implementation defined?  I can't get GCC to throw a warning and it was

Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting

2020-01-08 Thread Richard Henderson
On 1/9/20 11:49 AM, Palmer Dabbelt wrote: >> +    irqs = (pending & ~env->mideleg & -mie) | (pending &  env->mideleg & >> -sie); > > Isn't "-unsigned" implementation defined?  I can't get GCC to throw a warning > and it was already there, so maybe I'm just wrong? (1) You're confusing

Re: [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting

2020-01-08 Thread Palmer Dabbelt
On Mon, 09 Dec 2019 10:11:32 PST (-0800), Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 33 - 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index

[PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting

2019-12-09 Thread Alistair Francis
Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 33 - 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 63439c9370..85eed5d885 100644 --- a/target/riscv/cpu_helper.c +++