Re: [PATCH v1 23/43] target/loongarch: Add LoongArch interrupt and exception handle

On 4/15/22 02:40, Xiaojuan Yang wrote: +if (level) { +env->CSR_ESTAT |= 1 << irq; +} else { +env->CSR_ESTAT &= ~(1 << irq); +} This is env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0); +static inline unsigned int get_vint_size(CPULoongArchState

[PATCH v1 23/43] target/loongarch: Add LoongArch interrupt and exception handle

Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/cpu.c | 261 +++ target/loongarch/cpu.h | 2 + target/loongarch/internals.h | 2 + 3 files changed, 265 insertions(+) diff --git a/target/loongarch/cpu.c