This commit creates SPI controller to p10 chip and create the keystore seeprom device on spi_bus2 of PIB_SPIC[2].
Signed-off-by: Chalapathi V <chalapath...@linux.ibm.com> --- include/hw/ppc/pnv_chip.h | 4 ++++ hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 0ab5c42308..0d67516ede 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -4,6 +4,8 @@ #include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_spi_controller.h" +#include "hw/ppc/pnv_spi_seeprom.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -113,6 +115,8 @@ struct Pnv10Chip { PnvOCC occ; PnvSBE sbe; PnvHomer homer; +#define PNV10_CHIP_MAX_PIB_SPIC 6 + PnvSpiController pib_spic[PNV10_CHIP_MAX_PIB_SPIC]; uint32_t nr_quads; PnvQuad *quads; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..8fffd999f6 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1691,6 +1691,11 @@ static void pnv_chip_power10_instance_init(Object *obj) for (i = 0; i < pcc->i2c_num_engines; i++) { object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); } + + for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC ; i++) { + object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], + TYPE_PNV_SPI_CONTROLLER); + } } static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) @@ -1879,6 +1884,33 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_SBE_I2C)); } + + /* PIB SPI Controller */ + for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { + object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", + i , &error_fatal); + /* + * The TPM attached SPIC needs to reverse the bit order in each byte + * it sends to the TPM. + */ + if (i == 4) { + object_property_set_bool(OBJECT(&chip10->pib_spic[i]), + "reverse_bits", true, &error_fatal); + } + if (!qdev_realize(DEVICE(&chip10->pib_spic[i]), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + + i * PNV10_XSCOM_PIB_SPIC_SIZE, + &chip10->pib_spic[i].xscom_spic_regs); + } + + /* Primary MEAS/MVPD/Keystore SEEPROM connected to pib_spic[2]*/ + PnvSpiSeeprom *meas_mvpd_ks_p = PNV_SPI_SEEPROM(spi_create_responder( + (&chip10->pib_spic[2])->spi_bus, + TYPE_PNV_SPI_SEEPROM)); + meas_mvpd_ks_p->file = qemu_find_file(QEMU_FILE_TYPE_BIOS, + "sbe_measurement_seeprom.bin.ecc"); } static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) -- 2.31.1