[PATCH v10 09/61] target/riscv: add vector amo operations

2020-06-19 Thread LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PATCH v10 09/61] target/riscv: add vector amo operations

2020-06-19 Thread LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei Reviewed-by: Alistair