On Fri, 24 Jun 2022 16:01:42 +0100
Peter Maydell wrote:
> On Fri, 24 Jun 2022 at 15:54, Jonathan Cameron
> wrote:
> > Just occurred to me there is another barrier to an approach that adds
> > DT bindings.
> > I fairly sure hw/pci-bridge/pci_expander_bridge.c (PXB)
> > only works on ACPI
On Fri, 24 Jun 2022 at 15:54, Jonathan Cameron
wrote:
> Just occurred to me there is another barrier to an approach that adds
> DT bindings.
> I fairly sure hw/pci-bridge/pci_expander_bridge.c (PXB)
> only works on ACPI platforms and is the only host bridge supported
> for CXL emulation in QEMU.
On Fri, 24 Jun 2022 15:08:44 +0100
Jonathan Cameron wrote:
> On Fri, 24 Jun 2022 13:56:32 +0100
> Peter Maydell wrote:
>
> > On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
> > wrote:
> > >
> > > On Fri, 24 Jun 2022 11:48:47 +0100
> > > Peter Maydell wrote:
> > > >
> > > > This seems to
On Fri, 24 Jun 2022 13:56:32 +0100
Peter Maydell wrote:
> On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
> wrote:
> >
> > On Fri, 24 Jun 2022 11:48:47 +0100
> > Peter Maydell wrote:
> > >
> > > This seems to be missing code to advertise the new devices in the
> > > device tree.
> >
> >
On Fri, 24 Jun 2022 at 13:39, Jonathan Cameron
wrote:
>
> On Fri, 24 Jun 2022 11:48:47 +0100
> Peter Maydell wrote:
> >
> > This seems to be missing code to advertise the new devices in the
> > device tree.
>
> Intentionally. I am not aware of any current interest
> in defining DT support CXL or
On Fri, 24 Jun 2022 11:48:47 +0100
Peter Maydell wrote:
> On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
> wrote:
> >
> > Code based on i386/pc enablement.
> > The memory layout places space for 16 host bridge register regions after
> > the GIC_REDIST2 in the extended memmap.
> > The CFMWs are
On Thu, 16 Jun 2022 at 15:20, Jonathan Cameron
wrote:
>
> Code based on i386/pc enablement.
> The memory layout places space for 16 host bridge register regions after
> the GIC_REDIST2 in the extended memmap.
> The CFMWs are placed above the extended memmap.
>
> Only create the CEDT table if
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
---
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
