Hello, Thank You so much for reviewing patchset V1.
In PATCHSET V2, removed the PNV_SPI_RESPONDER model and an existing QEMU SSI framework is used to model SPI BUS and SEEPROM model and also most of Steve's comments have been addressed. Also added the pnv-spi-seeprom qtest is added to test to check SPI traffic between SPI controller and it's attached SEEPROM device. The new qom-tree looks like below. (qemu) info qom-tree /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[0] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.0 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[1] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.1 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[2] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.2 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[3] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.3 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[4] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.4 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[5] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.5 (SSI) /xscom-spi-controller-regs[0] (memory-region) /unattached (container) /device[7] (seeprom-25csm04) /ssi-gpio-cs[0] (irq) Patches overview in V2. PATCH1: Remove SPI responder model and used SSI framework instead. PATCH2: Create a SPI controller model and implement configuration unit to model SCOM registers. Move register constants to a seperate header file pnv_spi_controller_regs.h PATCH3: SPI controller model: implement sequencer FSM and shift engine. PATCH4: Create a Microchip's SEEPROM 25csm04 model using SSI framework and move it hw/misc as it is not a power specific device. PATCH5: Connect SPI controllers to p10 chip and create keystore seeprom device of type "seeprom-25csm04" and connect cs line PIB_SPIC[2]. PATCH6: Write a qtest pnv-spi-seeprom-test to check the SPI transactions between spi controller and seeprom device. Test covered: Ran make check. Thank You, Chalapathi Chalapathi V (6): hw/ppc: remove SPI responder model hw/ppc: SPI controller model - registers implementation hw/ppc: SPI controller model - sequencer and shifter hw/misc: Microchip's 25CSM04 SEEPROM model hw/ppc: SPI controller wiring to P10 chip and create seeprom device tests/qtest: Add pnv-spi-seeprom qtest include/hw/misc/seeprom_25csm04.h | 48 + include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_spi_controller.h | 127 ++ include/hw/ppc/pnv_spi_controller_regs.h | 114 ++ include/hw/ppc/pnv_xscom.h | 3 + hw/misc/seeprom_25csm04.c | 780 +++++++++++ hw/ppc/pnv.c | 36 +- hw/ppc/pnv_spi_controller.c | 1587 ++++++++++++++++++++++ tests/qtest/pnv-spi-seeprom-test.c | 126 ++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/ppc/Kconfig | 2 + hw/ppc/meson.build | 1 + tests/qtest/meson.build | 1 + 14 files changed, 2831 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/seeprom_25csm04.h create mode 100644 include/hw/ppc/pnv_spi_controller.h create mode 100644 include/hw/ppc/pnv_spi_controller_regs.h create mode 100644 hw/misc/seeprom_25csm04.c create mode 100644 hw/ppc/pnv_spi_controller.c create mode 100644 tests/qtest/pnv-spi-seeprom-test.c -- 2.39.3