Re: [PATCH v2 01/10] target/riscv/cpu.c: add zicntr extension flag

2023-10-12 Thread Daniel Henrique Barboza
On 10/10/23 23:51, Alistair Francis wrote: On Fri, Oct 6, 2023 at 11:23 PM Daniel Henrique Barboza wrote: zicntr is the Base Counters and Timers extension described in chapter 12 of the unprivileged spec. It describes support for RDCYCLE, RDTIME and RDINSTRET. QEMU already implements it

Re: [PATCH v2 01/10] target/riscv/cpu.c: add zicntr extension flag

2023-10-10 Thread Alistair Francis
On Fri, Oct 6, 2023 at 11:23 PM Daniel Henrique Barboza wrote: > > zicntr is the Base Counters and Timers extension described in chapter 12 > of the unprivileged spec. It describes support for RDCYCLE, RDTIME and > RDINSTRET. > > QEMU already implements it way before it was a discrete extension.

[PATCH v2 01/10] target/riscv/cpu.c: add zicntr extension flag

2023-10-06 Thread Daniel Henrique Barboza
zicntr is the Base Counters and Timers extension described in chapter 12 of the unprivileged spec. It describes support for RDCYCLE, RDTIME and RDINSTRET. QEMU already implements it way before it was a discrete extension. zicntr is part of the RVA22 profile, so let's add it to QEMU to make the