Hi, Richard.
On 07/23/2021 09:45 AM, Richard Henderson wrote:
>> +/* Fixed point load/store instruction translation */
>> +static bool trans_ld_b(DisasContext *ctx, arg_ld_b *a)
>> +{
>> + TCGv t0;
>> + TCGv Rd = cpu_gpr[a->rd];
>> + int mem_idx = ctx->mem_idx;
>> +
>> + if (a->rd ==
On 7/20/21 11:53 PM, Song Gao wrote:
This patch implement fixed point load/store instruction translation.
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
This patch implement fixed point load/store instruction translation.
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao
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