On 11/18/21 2:25 PM, Lucas Mateus Castro (alqotel) wrote:
+/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
+#define FPSCR_MTFS_MASK (~((1ull << 11) | FP_VX | FP_FEX))
If you're going to make the reserved bit 52 read-as-zero-writes-ignored, you should do the
same for reserved bits
On Thu, 18 Nov 2021, Lucas Mateus Castro (alqotel) wrote:
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
Although this is a difference reported in the bug, since
