Adding the high part of a minimal set of csr. Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org> --- target/riscv/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 81cbd77d09..a2d7d65efb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -196,9 +196,14 @@ struct CPURISCVState { target_ulong hgatp; uint64_t htimedelta; - /* Upper 64-bits of 128-bit misa CSR */ + /* Upper 64-bits of 128-bit CSRs */ uint64_t misah; uint64_t misah_mask; + uint64_t mtvech; + uint64_t mscratchh; + uint64_t mepch; + uint64_t satph; + uint64_t mstatush; /* Virtual CSRs */ /* -- 2.33.0