Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-04-21 Thread Palmer Dabbelt
On Tue, 21 Apr 2020 10:40:05 PDT (-0700), alistai...@gmail.com wrote: On Mon, Apr 20, 2020 at 7:17 PM Bin Meng wrote: On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis wrote: > > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng wrote: > > > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote: > > > >

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-04-21 Thread Alistair Francis
On Mon, Apr 20, 2020 at 7:17 PM Bin Meng wrote: > > On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis wrote: > > > > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng wrote: > > > > > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote: > > > > > > > > Hi Palmer, > > > > > > > > On Sat, Mar 7, 2020 at

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-04-20 Thread Bin Meng
On Tue, Apr 21, 2020 at 3:26 AM Alistair Francis wrote: > > On Wed, Apr 1, 2020 at 10:39 PM Bin Meng wrote: > > > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote: > > > > > > Hi Palmer, > > > > > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis > > > wrote: > > > > > > > > At present the

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-04-20 Thread Alistair Francis
On Wed, Apr 1, 2020 at 10:39 PM Bin Meng wrote: > > On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote: > > > > Hi Palmer, > > > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis > > wrote: > > > > > > At present the board serial number is hard-coded to 1, and passed > > > to OTP model during

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-04-03 Thread Palmer Dabbelt
On Mon, 23 Mar 2020 19:08:19 PDT (-0700), bmeng...@gmail.com wrote: Hi Palmer, On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis wrote: At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-04-01 Thread Bin Meng
On Tue, Mar 24, 2020 at 10:08 AM Bin Meng wrote: > > Hi Palmer, > > On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis > wrote: > > > > At present the board serial number is hard-coded to 1, and passed > > to OTP model during initialization. Firmware (FSBL, U-Boot) uses > > the serial number to

Re: [PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-03-23 Thread Bin Meng
Hi Palmer, On Sat, Mar 7, 2020 at 5:45 AM Alistair Francis wrote: > > At present the board serial number is hard-coded to 1, and passed > to OTP model during initialization. Firmware (FSBL, U-Boot) uses > the serial number to generate a unique MAC address for the on-chip > ethernet controller.

[PATCH v3 0/3] hw/riscv: Add a serial property to sifive_u

2020-03-06 Thread Alistair Francis
At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same