Hi Xiaoyao,
On Mon, Aug 07, 2023 at 04:13:36PM +0800, Xiaoyao Li wrote:
> Date: Mon, 7 Aug 2023 16:13:36 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v3 05/17] i386/cpu: Use APIC ID offset to encode cache
> topo in CPUID[4]
>
> On 8/1/2023 6:35 PM, Zhao Liu wrote:
On 8/1/2023 6:35 PM, Zhao Liu wrote:
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
I doubt it. Especially for [1].
SDM doesn't state it should be the
Hi Babu,
On Wed, Aug 02, 2023 at 10:41:17AM -0500, Moger, Babu wrote:
> Date: Wed, 2 Aug 2023 10:41:17 -0500
> From: "Moger, Babu"
> Subject: Re: [PATCH v3 05/17] i386/cpu: Use APIC ID offset to encode cache
> topo in CPUID[4]
>
> Hi Zhao,
>
> On 8/1/23 05:
Hi Zhao,
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
> CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
> nearest power-of-2 integer.
>
> The nearest power-of-2 integer can be caculated by
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be caculated by pow2ceil() or by
using APIC ID offset (like L3 topology using
