Re: [PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level

2022-10-11 Thread Alistair Francis
On Mon, Oct 3, 2022 at 2:16 PM Jim Shu wrote: > > The maximum priority level is hard-coded when writing to interrupt > priority register. However, when writing to priority threshold register, > the maximum priority level is from num_priorities Property which is > configured by platform. > > Also

[PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level

2022-10-02 Thread Jim Shu
The maximum priority level is hard-coded when writing to interrupt priority register. However, when writing to priority threshold register, the maximum priority level is from num_priorities Property which is configured by platform. Also change interrupt priority register to use num_priorities