Re: [PATCH v38 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions

2019-12-10 Thread Aleksandar Markovic
On Sun, Dec 8, 2019 at 7:40 PM Michael Rolnik wrote: > + > +/* > + * Performs the logical AND between the contents of register Rd and register > + * Rr and places the result in the destination register Rd. > + */ > +static bool trans_AND(DisasContext *ctx, arg_AND *a) > +{ > +TCGv Rd =

[PATCH v38 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions

2019-12-08 Thread Michael Rolnik
This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 734