Hey Andrew,
Sorry about the response delay, I was traveling.
On Fri, Jan 6, 2023 at 4:30 PM Andrew Jones wrote:
>
> On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at
On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Fri, Jan 06, 2023 at 08:56:33AM +0100, Alexandre Ghiti wrote:
> On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti
> wrote:
...
> @Andrew: Please let me know when you have some cycles to review this,
I'll try to get to this yet today. Thanks for the ping.
drew
On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote:
>
> Hi Frank,
>
> On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote:
> >
> > Hi Alexandre,
> >
> > Thanks for the contribution. This is really helpful.
> >
> > It seems like if we want to specify the SATP mode for the "named" CPUs,
> > we
Hi Frank,
On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote:
>
> Hi Alexandre,
>
> Thanks for the contribution. This is really helpful.
>
> It seems like if we want to specify the SATP mode for the "named" CPUs,
> we have to do, e.g.:
> cpu->cfg.satp_mode.map |= (1 <<
Hi Alexandre,
Thanks for the contribution. This is really helpful.
It seems like if we want to specify the SATP mode for the "named" CPUs,
we have to do, e.g.:
cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv39"));
in each CPU's init function.
Can we add another helper function to
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
