Re: [PATCH v4 0/3] pnv nest1 chiplet model

2023-11-11 Thread Cédric Le Goater
Hello Chalapathi, Please tune the "From: " email address of the series you send. This one uses " Chalapathi V " which is certainly from an internal IBM host. Unfortunately, we can not reply to this user/sender. On 11/7/23 08:41, Chalapathi V wrote: From: Chalapathi V Hello, For modularity

[PATCH v4 0/3] pnv nest1 chiplet model

2023-11-07 Thread Chalapathi V
From: Chalapathi V Hello, For modularity reasons the P10 processor chip is split into multiple chiplets individually controlled and managed by the pervasive logic. The boundaries of these chiplets are defined based on physical design parameters like clock grids, the nature of the functional