Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState

On 2020/2/11 23:53, Richard Henderson wrote: On 2/10/20 8:12 AM, LIU Zhiwei wrote: The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno,offset). Thus elements can be directly accessed by offset from the first vector

Re: [PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState

On 2/10/20 8:12 AM, LIU Zhiwei wrote: > The 32 vector registers will be viewed as a continuous memory block. > It avoids the convension between element index and (regno,offset). > Thus elements can be directly accessed by offset from the first vector > base address. > > Signed-off-by: LIU Zhiwei

[PATCH v4 1/4] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno,offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 13 + 1