Re: [PATCH v4 2/5] target/riscv: add vector stride load and store instructions

2020-03-06 Thread LIU Zhiwei
On 2020/2/28 3:36, Richard Henderson wrote: On 2/25/20 2:35 AM, LIU Zhiwei wrote: +GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t,

Re: [PATCH v4 2/5] target/riscv: add vector stride load and store instructions

2020-02-27 Thread LIU Zhiwei
On 2020/2/28 3:36, Richard Henderson wrote: On 2/25/20 2:35 AM, LIU Zhiwei wrote: +GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t,

Re: [PATCH v4 2/5] target/riscv: add vector stride load and store instructions

2020-02-27 Thread Richard Henderson
On 2/25/20 2:35 AM, LIU Zhiwei wrote: > +GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb) > +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb) > +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb) > +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t, int64_t, H8, ldsb) >

[PATCH v4 2/5] target/riscv: add vector stride load and store instructions

2020-02-25 Thread LIU Zhiwei
Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 35 +