On 12/3/19 3:48 AM, Peter Maydell wrote:
>> +{ .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
>> + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
>
> This should trap if HCR_EL2.TID5 is 1 (since we're
On Fri, 11 Oct 2019 at 14:48, Richard Henderson
wrote:
>
> This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
> RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.
>
> Signed-off-by: Richard Henderson
> ---
> v3: Add GMID; add access_mte.
> v4: Define only TCO at mte_insn_reg.
> ---
> target/arm/cpu.h
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.
Signed-off-by: Richard Henderson
---
v3: Add GMID; add access_mte.
v4: Define only TCO at mte_insn_reg.
---
target/arm/cpu.h | 3 ++
target/arm/internals.h | 6
