On Mon, Jul 13, 2020 at 10:39 AM Philippe Mathieu-Daudé wrote:
>
> On 7/12/20 7:42 AM, Havard Skinnemoen wrote:
> > On Thu, Jul 9, 2020 at 10:00 AM Philippe Mathieu-Daudé
> > wrote:
> >> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> >>> This implements a device model for the NPCM7xx SPI flash
On 7/12/20 7:42 AM, Havard Skinnemoen wrote:
> On Thu, Jul 9, 2020 at 10:00 AM Philippe Mathieu-Daudé
> wrote:
>> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
>>> This implements a device model for the NPCM7xx SPI flash controller.
>>>
>>> Direct reads and writes, and user-mode transactions have
On Thu, Jul 9, 2020 at 10:00 AM Philippe Mathieu-Daudé wrote:
>
> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> > This implements a device model for the NPCM7xx SPI flash controller.
> >
> > Direct reads and writes, and user-mode transactions have been tested in
> > various modes. Protection
On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> This implements a device model for the NPCM7xx SPI flash controller.
>
> Direct reads and writes, and user-mode transactions have been tested in
> various modes. Protection features are not implemented yet.
>
> All the FIU instances are available in
This implements a device model for the NPCM7xx SPI flash controller.
Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.
All the FIU instances are available in the SoC's address space,
regardless of whether or not
