Jonathan Cameron writes:
> On Fri, 27 Oct 2023 06:54:39 +0200
> Markus Armbruster wrote:
>
>> I'm trying to fill in QMP documentation holes, and found one in commit
>> 415442a1b4a (this patch). Details inline.
>>
>> Jonathan Cameron writes:
>>
>> > CXL uses PCI AER Internal errors to signal
On Fri, 27 Oct 2023 06:54:39 +0200
Markus Armbruster wrote:
> I'm trying to fill in QMP documentation holes, and found one in commit
> 415442a1b4a (this patch). Details inline.
>
> Jonathan Cameron writes:
>
> > CXL uses PCI AER Internal errors to signal to the host that an error has
> >
I'm trying to fill in QMP documentation holes, and found one in commit
415442a1b4a (this patch). Details inline.
Jonathan Cameron writes:
> CXL uses PCI AER Internal errors to signal to the host that an error has
> occurred. The host can then read more detailed status from the CXL RAS
>
Philippe Mathieu-Daudé writes:
> On 23/2/23 15:27, Jonathan Cameron wrote:
>> On Thu, 23 Feb 2023 08:37:46 +0100
>> Markus Armbruster wrote:
>>> Whenever you use a poisoned macro in a conditional, all the code
>>> generated for this .json file (we call it a "QAPI schema module")
>>> becomes
On 23/2/23 15:27, Jonathan Cameron wrote:
On Thu, 23 Feb 2023 08:37:46 +0100
Markus Armbruster wrote:
Thomas Huth writes:
On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
+Thomas (meson) & Marc-André (conditional QAPI)
+ Markus
On 22/2/23 17:49, Jonathan Cameron wrote:
[...]
On Thu, 23 Feb 2023 14:27:48 +
Jonathan Cameron wrote:
> On Thu, 23 Feb 2023 08:37:46 +0100
> Markus Armbruster wrote:
>
> > Thomas Huth writes:
> >
> > > On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> > >> +Thomas (meson) & Marc-André (conditional QAPI)
> > >
> > > +
On Thu, 23 Feb 2023 08:37:46 +0100
Markus Armbruster wrote:
> Thomas Huth writes:
>
> > On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
> >> +Thomas (meson) & Marc-André (conditional QAPI)
> >
> > + Markus
> >
> >> On 22/2/23 17:49, Jonathan Cameron wrote:
>
> [...]
>
> >>
Thomas Huth writes:
> On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
>> +Thomas (meson) & Marc-André (conditional QAPI)
>
> + Markus
>
>> On 22/2/23 17:49, Jonathan Cameron wrote:
[...]
>> Doesn't these need
>>
>> 'if': 'CONFIG_CXL_MEM_DEVICE',
>>
>> ?
>
On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
+Thomas (meson) & Marc-André (conditional QAPI)
+ Markus
On 22/2/23 17:49, Jonathan Cameron wrote:
+# Type of uncorrectable CXL error to inject. These errors are
reported via
+# an AER uncorrectable internal error with additional
Jonathan Cameron writes:
> On Tue, 21 Feb 2023 23:15:49 +0100
> Philippe Mathieu-Daudé wrote:
>
>> Hi Jonathan,
>>
>> On 21/2/23 16:21, Jonathan Cameron wrote:
>> > CXL uses PCI AER Internal errors to signal to the host that an error has
>> > occurred. The host can then read more detailed
+Thomas (meson) & Marc-André (conditional QAPI)
On 22/2/23 17:49, Jonathan Cameron wrote:
+# Type of uncorrectable CXL error to inject. These errors are reported via
+# an AER uncorrectable internal error with additional information logged at
+# the CXL device.
+#
+# @cache-data-parity: Data
...
> >>> +# Type of uncorrectable CXL error to inject. These errors are reported
> >>> via
> >>> +# an AER uncorrectable internal error with additional information logged
> >>> at
> >>> +# the CXL device.
> >>> +#
> >>> +# @cache-data-parity: Data error such as data parity or data ECC error
On 22/2/23 15:53, Jonathan Cameron wrote:
On Tue, 21 Feb 2023 23:15:49 +0100
Philippe Mathieu-Daudé wrote:
Hi Jonathan,
On 21/2/23 16:21, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status
On Tue, 21 Feb 2023 23:15:49 +0100
Philippe Mathieu-Daudé wrote:
> Hi Jonathan,
>
> On 21/2/23 16:21, Jonathan Cameron wrote:
> > CXL uses PCI AER Internal errors to signal to the host that an error has
> > occurred. The host can then read more detailed status from the CXL RAS
> > capability.
>
Hi Jonathan,
On 21/2/23 16:21, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is
On 2/21/23 8:21 AM, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in
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